To run the Xi6 design on an FPC2 the xilinx chip needs to be connected to two additional data bits. This is a compatible upgrade which uses two previously unconnected pins on the xilinx chip, and so it is still possible to use the older Xi3 design. Pin 2 on the xilinx (also known as A2) should be connected to data bit 26. This is best achieved by soldering to the via on the back of the board near where that signal attaches to SRAM[3] pin 13. Pin 3 on the xilinx (also known as A3) should be connected to data bit 27. This is best achieved by soldering to the via on the back of the board near where that signal attaches to WR[3] pin 16.