Sigmetrics/Performance 2012 Hands-on tutorial-workshop

Abstract

The NetFPGA is and open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, attendees will learn about the NetFPGA platform and and how it can be used. We will demonstrate the use of the reference router to dynamically re-route traffic using PW-OSPF with streaming video traffic. We will also show how we can extend existing designs to experiment with buffer sizes.

No knowledge of Verilog/VHDL is required to attend the tutorial, although knowledge of these languages is needed to program NetFPGA.

Outline

• Introduction to the Platform

  • Users (Professors & Researchers)

  • What is the NetFPGA

    • Board
    • Tools & Reference Designs
    • Contributed Projects
    • Community

• Hardware Overview

  • NetFPGA 1G

    • Gigabit Ethernet interfaces
    • Field Programmable Gate Array (FPGA) Logic
    • Random Access Memory (RAM)
    • PCI interface

  • NetFPGA 10G

    • SPF+ interfaces
    • Field Programmable Gate Array (FPGA) Logic
    • Random Access Memory (RAM)
    • PCIe interface

• Brief recap if IP/Routing

• Example 1: Basic Functionality (reference router)

  • PW-OSPF

  • Routing Tables

  • Dynamic re-routing

• Example 2: Advanced Functionality (buffer sizing based on reference router)

  • Brief introduction of buffer sizing

    • Rule-of-thumb for the buffer size
    • Round-trip propation delay
    • Capacity of bottlneck link
    • Number of active flows

  • Additional hardware

    • Event capture module
    • Rate limiter

  • Experiments

    • Netperf
    • HD video transport

  Where to get started/What to do next

  • Webpage

  • Wiki

  • Forums

About the presenters

• Andrew W. Moore
  is a Senior Lecturer at the University of Cambridge Computer Laboratory. He joined the permanent faculty of Cambridge in 2007, prior to this he had been an EPSRC Roberts Fellow at Queen Mary, University of London, an Intel Research Fellow in Cambridge and foundation-researcher at the Cambridge Marconi research laboratory. Throughout this time Andrew has focused upon network characterisation and measurement, extensible monitoring for application performance-analysis and large-scale Internet monitoring and emulation. Interest in switch design has led to work in physical line-coding for optical networks, and novel optical-switch architectures.

  Andrew completed his Ph.D. with the Cambridge University Computer Laboratory in 2001 and prior to that took a Masters degree and an honours degree from Monash University in Melbourne. Australia. Alongside routine collaboration with AT&T, Endace, Intel, and Microsoft, Andrew Moore has served as principal investigator on grants from the UK Research Council (EPSRC), a number of other UK government bodies and acts as investigator on two DARPA grants. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.

  Andrew lead the recently completed Alpha-user programme for the new, 10Gbps NetFPGA.

• Paolo Costa
  Paolo Costa holds a fellowship at the Department of Computing of Imperial College London. Before joining Imperial, he spent 2.5 years in the Systems and Networking Group of the Microsoft Research Lab in Cambridge and, prior to that, he had been a Postdoctoral Researcher in the Computer Systems group at Vrije Universiteit Amsterdam. He holds a M. Sc. and Ph.D. degree in Computer Engineering from the Politecnico di Milano, received, respectively, in 2002 and 2006. His research interests lie at the intersection of systems and networking with particular focus on large-scale networked systems, ranging from sensor and mobile networks to overlays and, more recently, data centers.

Registration

• Registration for the tutorial is now on-line from the link on the Sigmetrics/Performance 2012 website.
• The NetFPGA tutorial is part of the Affiliated Workshop Program. To register for NetFPGA Hands-on Tutorial, please go through the Sigmetrics/Performance registration page.

Tutorial Material

• 2-up PDF of slides
• PPT