=== Work directory is /tmp/root/verif/filter_nic.
=== Calling make to build simulation binary with
cd /tmp/root/verif/filter_nic; rm -rf my_sim; make -f Makefile DUMP_CTRL= SIM_OPT=  vsim_top
make -C /root/NF2-filter_nic/projects/filter_nic/synth cores
make[1]: Entering directory `/root/NF2-filter_nic/projects/filter_nic/synth'
Made cores.
make[1]: Leaving directory `/root/NF2-filter_nic/projects/filter_nic/synth'
make -C /root/NF2/projects/CPCI_2.1/synth cores
make[1]: Entering directory `/root/NF2/projects/CPCI_2.1/synth'
Made cores.
make[1]: Leaving directory `/root/NF2/projects/CPCI_2.1/synth'
===============================================================================
Building ModelSim binary
===============================================================================
+++testStarted:build.ModelSim.binary
UNET_EXTRA_DIRS is
# Create the behavioral directory
cd vsim_beh &&  vlog +notimingchecks -incr +define+sg5E +define+x16 +define+MAX_MEM +define+sb166 +libext+.v  +define+VSIM_COMPILE  +incdir+/root/NF2/lib/verilog/common/src21+/root/NF2/lib/verilog/testbench+/root/NF2-filter_nic/projects/filter_nic/include+++ \
	-y /root/NF2-filter_nic/projects/filter_nic/src  -y /root/NF2/projects/CPCI_2.1/src -y /root/NF2/projects/CPCI_2.1/src/src_coregen -y /usr/local/Xilinx91i/verilog/src/simprims -y /usr/local/Xilinx91i/verilog/src/unisims -v /usr/local/Xilinx91i/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v -y /usr/local/Xilinx91i/verilog/src/XilinxCoreLib -y /usr/local/Xilinx91i/smartmodel/lin/wrappers/mtiverilog  -y /root/NF2/lib/verilog/common/src21 -y /root/NF2/lib/verilog/testbench -v /root/NF2/projects/CPCI_2.1/src/src_coregen/pci_lc_i.v -y /root/NF2/lib/verilog/common/src21  /root/NF2/lib/verilog/common/src21/global_defines.v /root/NF2-filter_nic/projects/filter_nic/include/crypto_defines.v /root/NF2-filter_nic/projects/filter_nic/include/dev_id.v /root/NF2/lib/verilog/common/src21/global_defines.v /root/NF2/lib/verilog/common/src21/cpci_defines.v /root/NF2/lib/verilog/common/src21/NF_2.1_defines.v /root/NF2/lib/verilog/common/src21/udp_defines.v /root/NF2-filter_nic/projects/filter_nic/include/crypto_defines.v /root/NF2-filter_nic/projects/filter_nic/include/dev_id.v /root/NF2-filter_nic/projects/filter_nic/src/blockram.v /root/NF2-filter_nic/projects/filter_nic/src/decision.v /root/NF2-filter_nic/projects/filter_nic/src/flowlookup.v /root/NF2-filter_nic/projects/filter_nic/src/fxpf.v /root/NF2-filter_nic/projects/filter_nic/src/hashgen.v /root/NF2-filter_nic/projects/filter_nic/src/l3l4extract.v /root/NF2-filter_nic/projects/filter_nic/src/user_data_path.v    /root/NF2/lib/verilog/io_queues/cpu_dma_queue/src/cpu_dma_queue_main.v /root/NF2/lib/verilog/io_queues/cpu_dma_queue/src/cpu_dma_queue_regs.v /root/NF2/lib/verilog/io_queues/cpu_dma_queue/src/cpu_dma_queue.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/mac_grp_regs.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/nf2_mac_grp.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/rx_queue.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/tx_queue.v /root/NF2/lib/verilog/input_arbiter/rr_input_arbiter/src/in_arb_regs.v /root/NF2/lib/verilog/input_arbiter/rr_input_arbiter/src/input_arbiter.v /root/NF2/lib/verilog/nf2/generic_top/src/dump.v /root/NF2/lib/verilog/nf2/generic_top/src/nf2_top.v /root/NF2/lib/verilog/nf2/generic_top/src/rgmii_io.v /root/NF2/lib/verilog/nf2/reference_core/src/nf2_core.v /root/NF2/lib/verilog/nf2/reference_core/src/nf2_reg_grp.v /root/NF2/lib/verilog/user_data_path/generic_cntr_reg/src/generic_cntr_reg.v /root/NF2/lib/verilog/output_port_lookup/nic/src/output_port_lookup.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_header_parser.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_reg_helper.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_reg_instances.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs_ctrl.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs_dual_port_ram.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs_eval_empty.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs_eval_full.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs_generic_reg_grp.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs_host_iface.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/oq_regs.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/output_queues.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/remove_pkt.v /root/NF2/lib/verilog/output_queues/sram_rr_output_queues/src/store_pkt.v /root/NF2/lib/verilog/sram_arbiter/sram_weighted_rr/src/cnet_sram_sm.v /root/NF2/lib/verilog/sram_arbiter/sram_weighted_rr/src/sram_arbiter.v /root/NF2/lib/verilog/sram_arbiter/sram_weighted_rr/src/sram_reg_access.v /root/NF2/lib/verilog/user_data_path/reference_user_data_path/src/udp_reg_grp.v /root/NF2/lib/verilog/io/mdio/src/nf2_mdio.v /root/NF2/lib/verilog/cpci_bus/src/cpci_bus.v /root/NF2/lib/verilog/dma/src/nf2_dma_bus_fsm.v /root/NF2/lib/verilog/dma/src/nf2_dma_que_intfc.v /root/NF2/lib/verilog/dma/src/nf2_dma_sync.v /root/NF2/lib/verilog/dma/src/nf2_dma.v /root/NF2/lib/verilog/user_data_path/udp_reg_master/src/udp_reg_master.v /root/NF2/lib/verilog/io_queues/add_rm_hdr/src/add_hdr.v /root/NF2/lib/verilog/io_queues/add_rm_hdr/src/add_rm_hdr.v /root/NF2/lib/verilog/io_queues/add_rm_hdr/src/rm_hdr.v /root/NF2/lib/verilog/strip_headers/keep_length/src/strip_headers.v /root/NF2/lib/verilog/utils/generic_regs/src/generic_cntr_regs.v /root/NF2/lib/verilog/utils/generic_regs/src/generic_hw_regs.v /root/NF2/lib/verilog/utils/generic_regs/src/generic_regs.v /root/NF2/lib/verilog/utils/generic_regs/src/generic_sw_regs.v /root/NF2/lib/verilog/utils/src/decoder.v /root/NF2/lib/verilog/utils/src/device_id_reg.v /root/NF2/lib/verilog/utils/src/fallthrough_small_fifo.v /root/NF2/lib/verilog/utils/src/lfsr32.v /root/NF2/lib/verilog/utils/src/priority_encoder.v /root/NF2/lib/verilog/utils/src/pulse_synchronizer.v /root/NF2/lib/verilog/utils/src/reg_grp.v /root/NF2/lib/verilog/utils/src/small_async_fifo.v /root/NF2/lib/verilog/utils/src/small_fifo.v /root/NF2/lib/verilog/utils/src/unused_reg.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/src_coregen/rxfifo_8kx9_to_36.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/src_coregen/rxfifo_8kx9_to_72.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/src_coregen/rxlengthfifo_128x13.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/src_coregen/tri_mode_eth_mac.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/src_coregen/txfifo_1024x36_to_9.v /root/NF2/lib/verilog/io_queues/ethernet_mac/src/src_coregen/txfifo_512x72_to_9.v /root/NF2/lib/verilog/cpci_bus/src/src_coregen/net2pci_16x32.v /root/NF2/lib/verilog/cpci_bus/src/src_coregen/pci2net_16x60.v /root/NF2/lib/verilog/dma/src/src_coregen/syncfifo_512x32.v /root/NF2/lib/verilog/io_queues/add_rm_hdr/src/src_coregen/hdr_fifo.v /root/NF2/lib/verilog/utils/src/src_coregen/async_fifo_256x72_to_36.v /root/NF2/lib/verilog/utils/src/src_coregen/async_fifo_512x36_progfull_500.v /root/NF2/lib/verilog/utils/src/src_coregen/async_fifo_512x36_to_72_progfull_500.v /root/NF2/lib/verilog/utils/src/src_coregen/syncfifo_512x36.v /root/NF2/lib/verilog/utils/src/src_coregen/syncfifo_512x72.v /root/NF2/lib/verilog/testbench/testbench.v /root/NF2-filter_nic/projects/filter_nic/src/ /usr/local/Xilinx91i/verilog/src/glbl.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Skipping module blockram
-- Skipping module decision
-- Skipping module flowlookup
-- Skipping module fxpf
-- Skipping module hashgen
-- Skipping module hashgen_crcnet
-- Skipping module l3l4extract
-- Skipping module user_data_path
-- Skipping module cpu_dma_queue_main
-- Skipping module cpu_dma_queue_regs
-- Skipping module cpu_dma_queue
-- Skipping module mac_grp_regs
-- Skipping module nf2_mac_grp
-- Skipping module rx_queue
-- Skipping module tx_queue
-- Skipping module in_arb_regs
-- Skipping module input_arbiter
-- Skipping module dump
-- Skipping module nf2_top
-- Skipping module rgmii_io
-- Skipping module nf2_core
-- Skipping module nf2_reg_grp
-- Skipping module generic_cntr_reg
-- Skipping module output_port_lookup
-- Skipping module oq_header_parser
-- Skipping module oq_reg_helper
-- Skipping module oq_reg_instances
-- Skipping module oq_regs_ctrl
-- Skipping module oq_regs_dual_port_ram
-- Skipping module oq_regs_eval_empty
-- Skipping module oq_regs_eval_full
-- Skipping module oq_regs_generic_reg_grp
-- Skipping module oq_regs_host_iface
-- Skipping module oq_regs
-- Skipping module output_queues
-- Skipping module remove_pkt
-- Skipping module store_pkt
-- Skipping module cnet_sram_sm
-- Skipping module sram_arbiter
-- Skipping module sram_reg_access
-- Skipping module udp_reg_grp
-- Skipping module nf2_mdio
-- Skipping module cpci_bus
-- Skipping module nf2_dma_bus_fsm
-- Skipping module nf2_dma_que_intfc
-- Skipping module nf2_dma_sync
-- Skipping module nf2_dma
-- Skipping module udp_reg_master
-- Skipping module add_hdr
-- Skipping module add_rm_hdr
-- Skipping module rm_hdr
-- Skipping module strip_headers
-- Skipping module generic_cntr_regs
-- Skipping module generic_hw_regs
-- Skipping module generic_regs
-- Skipping module generic_sw_regs
-- Skipping module decoder
-- Skipping module device_id_reg
-- Skipping module fallthrough_small_fifo
-- Skipping module lfsr32
-- Skipping module priority_encoder
-- Skipping module pulse_synchronizer
-- Skipping module reg_grp
-- Skipping module small_async_fifo
-- Skipping module sync_r2w
-- Skipping module sync_w2r
-- Skipping module rptr_empty
-- Skipping module wptr_full
-- Skipping module fifo_mem
-- Skipping module small_fifo
-- Skipping module unused_reg
-- Skipping module rxfifo_8kx9_to_36
-- Skipping module rxfifo_8kx9_to_72
-- Skipping module rxlengthfifo_128x13
-- Skipping module tri_mode_eth_mac
-- Compiling module glbl
-- Skipping module txfifo_1024x36_to_9
-- Skipping module txfifo_512x72_to_9
-- Skipping module net2pci_16x32
-- Skipping module pci2net_16x60
-- Skipping module syncfifo_512x32
-- Skipping module hdr_fifo
-- Skipping module async_fifo_256x72_to_36
-- Skipping module async_fifo_512x36_progfull_500
-- Skipping module async_fifo_512x36_to_72_progfull_500
-- Skipping module syncfifo_512x36
-- Skipping module syncfifo_512x72
-- Skipping module testbench
** Warning: /usr/local/Xilinx91i/verilog/src/glbl.v(5): 'glbl' already exists and will be overwritten.
-- Compiling module glbl
-- Scanning library directory '/root/NF2-filter_nic/projects/filter_nic/src'
-- Scanning library directory '/root/NF2/projects/CPCI_2.1/src'
-- Scanning library directory '/root/NF2/projects/CPCI_2.1/src/src_coregen'
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/simprims'
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/unisims'
-- Skipping module IBUF
-- Skipping module DCM
-- Skipping module dcm_clock_divide_by_2
-- Skipping module dcm_maximum_period_check
-- Skipping module dcm_clock_lost
-- Skipping module BUFGMUX
-- Skipping module IBUFG
-- Skipping module FDDRRSE
-- Skipping module OBUF
-- Skipping module INV
-- Skipping module VCC
-- Skipping module GND
-- Skipping module LUT3_L
-- Skipping module LUT4_D
-- Skipping module LUT4_L
-- Skipping module LUT3_D
-- Skipping module LUT2_D
-- Skipping module MUXF5
-- Skipping module LUT4
-- Skipping module LUT3
-- Skipping module LUT2
-- Skipping module FDCE
-- Skipping module FDCPE
-- Skipping module LUT1
-- Skipping module MUXCY
-- Skipping module FDP
-- Skipping module FDC
-- Skipping module FDPE
-- Skipping module XORCY
-- Skipping module FDE
-- Skipping module MUXCY_L
-- Skipping module AND2
-- Skipping module SRL16E
-- Skipping module FDRE
-- Skipping module SRL16
-- Scanning library file '/usr/local/Xilinx91i/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v'
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/XilinxCoreLib'
-- Skipping module FIFO_GENERATOR_V3_2
-- Skipping module fifo_generator_v3_2_bhv_ver_as
-- Skipping module fifo_generator_v3_2_bhv_ver_ss
-- Skipping module fifo_generator_v3_2_bhv_ver_preload0
-- Skipping module FIFO_GENERATOR_V3_3
-- Skipping module fifo_generator_v3_3_bhv_ver_as
-- Skipping module fifo_generator_v3_3_bhv_ver_ss
-- Skipping module fifo_generator_v3_3_bhv_ver_preload0
-- Scanning library directory '/usr/local/Xilinx91i/smartmodel/lin/wrappers/mtiverilog'
-- Scanning library directory '/root/NF2/lib/verilog/common/src21'
-- Scanning library directory '/root/NF2/lib/verilog/testbench'
-- Skipping module u_board
-- Skipping module phy_mdio_port
-- Skipping module host32
-- Skipping module target32
-- Skipping module net
-- Skipping module cpci_program_iface
-- Scanning library file '/root/NF2/projects/CPCI_2.1/src/src_coregen/pci_lc_i.v'
-- Scanning library directory '/root/NF2/lib/verilog/common/src21'
** Warning: /root/NF2/lib/verilog/common/src21/cy7c1370.v(100): [TMREN] - Redefinition of macro: teohz.
** Warning: /root/NF2/lib/verilog/common/src21/cy7c1370.v(102): [TMREN] - Redefinition of macro: tchz.
** Warning: /root/NF2/lib/verilog/common/src21/cy7c1370.v(105): [TMREN] - Redefinition of macro: tco.
** Warning: /root/NF2/lib/verilog/common/src21/cy7c1370.v(108): [TMREN] - Redefinition of macro: tas.
** Warning: /root/NF2/lib/verilog/common/src21/cy7c1370.v(109): [TMREN] - Redefinition of macro: tah.
-- Skipping module cy7c1370
-- Skipping module ddr2
-- Scanning library directory '/root/NF2-filter_nic/projects/filter_nic/src'
-- Scanning library directory '/root/NF2/projects/CPCI_2.1/src'
-- Skipping module cpci_top
-- Skipping module cpci_clock_checker
-- Skipping module pcim_top
-- Skipping module reg_file
-- Skipping module cnet_reg_access
-- Skipping module cnet_reg_iface
-- Skipping module cnet_reprogram
-- Skipping module cnet_dma_bus_master
-- Skipping module dma_engine
-- Skipping module cpci_heartbeat
-- Skipping module cfg
-- Skipping module pci_userapp
-- Skipping module fifo_8x32
-- Skipping module dma_read_fifo_4x32
-- Skipping module dma_engine_ctrl
-- Skipping module dma_engine_rr_arb
-- Skipping module dma_engine_pci_xfer
-- Skipping module dma_engine_alignment
-- Skipping module dma_engine_cntr
-- Scanning library directory '/root/NF2/projects/CPCI_2.1/src/src_coregen'
-- Skipping module pcim_lc
-- Skipping module cpci_pci2net_16x60
-- Skipping module pci2net_dma_16x32
-- Skipping module net2pci_dma_512x32
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/simprims'
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/unisims'
-- Skipping module BUFGDLL
-- Skipping module IOBUF_PCI33_3
-- Skipping module OBUFT_PCI33_3
-- Skipping module IBUF_PCI33_3
-- Skipping module IBUFG_PCI33_3
-- Skipping module BUFG
-- Skipping module CLKDLL
-- Skipping module clkdll_maximum_period_check
-- Scanning library file '/usr/local/Xilinx91i/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v'
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/XilinxCoreLib'
-- Scanning library directory '/usr/local/Xilinx91i/smartmodel/lin/wrappers/mtiverilog'
-- Scanning library directory '/root/NF2/lib/verilog/common/src21'
-- Scanning library directory '/root/NF2/lib/verilog/testbench'
-- Scanning library file '/root/NF2/projects/CPCI_2.1/src/src_coregen/pci_lc_i.v'
-- Skipping module PCI_LC_I
-- Scanning library directory '/root/NF2/lib/verilog/common/src21'
-- Scanning library directory '/root/NF2-filter_nic/projects/filter_nic/src'
-- Scanning library directory '/root/NF2/projects/CPCI_2.1/src'
-- Scanning library directory '/root/NF2/projects/CPCI_2.1/src/src_coregen'
-- Scanning library directory '/usr/local/Xilinx91i/verilog/src/simprims'
-- Skipping module X_INV
-- Skipping module X_BUF
-- Skipping module X_OR2
-- Skipping module X_AND2
-- Skipping module X_OR3
-- Skipping module X_AND3
-- Skipping module X_FF
-- Skipping UPD ffsrce
-- Skipping module X_PU
-- Skipping module X_AND4
-- Skipping module X_MUX2
-- Skipping UPD mux
-- Skipping module X_ZERO
-- Skipping module X_OR4
-- Skipping module X_ONE
-- Skipping module X_AND5
-- Skipping module X_XOR2
-- Skipping module X_TRI
-- Skipping module X_XOR4
-- Skipping module X_XOR3
-- Scanning library file '/usr/local/Xilinx91i/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v'
-- Scanning library file '/root/NF2/projects/CPCI_2.1/src/src_coregen/pci_lc_i.v'

Top level modules:
	dump
	generic_cntr_reg
	oq_reg_helper
	udp_reg_grp
	strip_headers
	decoder
	lfsr32
	priority_encoder
	glbl
	testbench
touch model_sim
+++testFinished:build.ModelSim.binary
=== Simulation compiled.
reg_defines.h -> reg_defines.ph
reg_defines_filter_nic.h -> reg_defines_filter_nic.ph
=== Will run the following tests:
test_nic_short 


=== Setting up simulation in /tmp/root/verif/filter_nic/test_nic_short...
=== Copying files to test directory /tmp/root/verif/filter_nic/test_nic_short.
=== Running test /tmp/root/verif/filter_nic/test_nic_short/test_nic_short ...
--- Reading configuration file
Seen: test_desc => Simple NIC test
Seen: finish => 20000
--- Running test.
Simple NIC test
--- Generating packets...
00 11 11 11 11 11 00 22 22 22 22 22 08 00 45 00 00 28 00 00 00 00 40 06 f9 82 c0 a8 00 02 c0 a8 00 01 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 
--- make_pkts.pl: Generated all configuration packets.
--- make_pkts.pl: Last packet enters system at approx 5 microseconds.
--- Running the simulation (takes a while). Logging to my_sim.log
--- Running vsim
Reading /usr/local/modelsim64/modeltech/tcl/vsim/pref.tcl 
--- Simulation is complete. Cannot evaluate correctness due to GUI mode.
Test test_nic_short passed!
------------SUMMARY---------------
PASSING TESTS: 
		test_nic_short
FAILING TESTS: 
TOTAL: 1 PASS: 1  FAIL: 0
reg_defines_filter_nic.h -> reg_defines_filter_nic.ph
