// CBG Orangepath HPRLS System // Verilog output file generated at Fri Jul 25 16:15:47 BST 2008 // hpr/ls $Id: hprls_sml_lib.sml,v 1.34 2008/07/09 10:23:53 djg11 Exp $ // -no-clear-arrays -root BVCI_BRIDGE_FOURPORT -vnl bvci_bridge_fourport.v module bvci_bridge_fourport(reset, port_inA_netside_address, port_inA_netside_be, port_inA_netside_cmd, port_inA_netside_eop, port_inA_netside_plen, port_inA_netside_wdata, port_inA_netside_cmdval, port_inA_netside_cmdack, port_inA_netside_rspval, port_inA_netside_rspack, port_inA_netside_bgt_rerror, port_inA_netside_rdata, port_inA_netside_reop, port_inA_netside_rerror, port_inA_write_wrbuf, port_inA_write_wrlen, port_inA_write_wraddr, port_inB_netside_address, port_inB_netside_be, port_inB_netside_cmd, port_inB_netside_eop, port_inB_netside_plen, port_inB_netside_wdata, port_inB_netside_cmdval, port_inB_netside_cmdack, port_inB_netside_rspval, port_inB_netside_rspack, port_inB_netside_bgt_rerror, port_inB_netside_rdata, port_inB_netside_reop, port_inB_netside_rerror, port_inB_write_wrbuf, port_inB_write_wrlen, port_inB_write_wraddr, port_inB_read_rdbuf, port_inB_read_rdlen, port_inB_read_rdaddr, port_outC_netside_address, port_outC_netside_be, port_outC_netside_cmd, port_outC_netside_eop, port_outC_netside_plen, port_outC_netside_wdata, port_outC_netside_cmdval, port_outC_netside_cmdack, port_outC_netside_rspval, port_outC_netside_rspack, port_outC_netside_bgt_rerror, port_outC_netside_rdata, port_outC_netside_reop, port_outC_netside_rerror, port_outC_write_wrbuf, port_outC_write_wrlen, port_outC_write_wraddr, port_outC_read_rdbuf, port_outC_read_rdlen, port_outC_read_rdaddr, port_outD_netside_address, port_outD_netside_be, port_outD_netside_cmd, port_outD_netside_eop, port_outD_netside_plen, port_outD_netside_wdata, port_outD_netside_cmdval, port_outD_netside_cmdack, port_outD_netside_rspval, port_outD_netside_rspack, port_outD_netside_bgt_rerror, port_outD_netside_rdata, port_outD_netside_reop, port_outD_netside_rerror, port_outD_write_wrbuf, port_outD_write_wrlen, port_outD_write_wraddr, port_outD_read_rdbuf, port_outD_read_rdlen, port_outD_read_rdaddr, clk, port_inA_read_rdbuf, port_inA_read_rdlen, port_inA_read_rdaddr, reset, clk); input reset; input [31:0] port_inA_netside_address; input [3:0] port_inA_netside_be; input [3:0] port_inA_netside_cmd; input port_inA_netside_eop; input [7:0] port_inA_netside_plen; input [31:0] port_inA_netside_wdata; input port_inA_netside_cmdval; output port_inA_netside_cmdack; output port_inA_netside_rspval; input port_inA_netside_rspack; output port_inA_netside_bgt_rerror; output [31:0] port_inA_netside_rdata; output port_inA_netside_reop; output port_inA_netside_rerror; input port_inA_write_wrbuf; input port_inA_write_wrlen; input port_inA_write_wraddr; input [31:0] port_inB_netside_address; input [3:0] port_inB_netside_be; input [3:0] port_inB_netside_cmd; input port_inB_netside_eop; input [7:0] port_inB_netside_plen; input [31:0] port_inB_netside_wdata; input port_inB_netside_cmdval; output port_inB_netside_cmdack; output port_inB_netside_rspval; input port_inB_netside_rspack; output port_inB_netside_bgt_rerror; output [31:0] port_inB_netside_rdata; output port_inB_netside_reop; output port_inB_netside_rerror; input port_inB_write_wrbuf; input port_inB_write_wrlen; input port_inB_write_wraddr; input [31:0] port_inB_read_rdbuf; input [7:0] port_inB_read_rdlen; input [31:0] port_inB_read_rdaddr; output [31:0] port_outC_netside_address; output [3:0] port_outC_netside_be; output [3:0] port_outC_netside_cmd; output port_outC_netside_eop; output [7:0] port_outC_netside_plen; output [31:0] port_outC_netside_wdata; output port_outC_netside_cmdval; input port_outC_netside_cmdack; input port_outC_netside_rspval; output port_outC_netside_rspack; input port_outC_netside_bgt_rerror; input [31:0] port_outC_netside_rdata; input port_outC_netside_reop; input port_outC_netside_rerror; input port_outC_write_wrbuf; input port_outC_write_wrlen; input port_outC_write_wraddr; input [31:0] port_outC_read_rdbuf; input [7:0] port_outC_read_rdlen; input [31:0] port_outC_read_rdaddr; output [31:0] port_outD_netside_address; output [3:0] port_outD_netside_be; output [3:0] port_outD_netside_cmd; output port_outD_netside_eop; output [7:0] port_outD_netside_plen; output [31:0] port_outD_netside_wdata; output port_outD_netside_cmdval; input port_outD_netside_cmdack; input port_outD_netside_rspval; output port_outD_netside_rspack; input port_outD_netside_bgt_rerror; input [31:0] port_outD_netside_rdata; input port_outD_netside_reop; input port_outD_netside_rerror; input port_outD_write_wrbuf; input port_outD_write_wrlen; input port_outD_write_wraddr; input [31:0] port_outD_read_rdbuf; input [7:0] port_outD_read_rdlen; input [31:0] port_outD_read_rdaddr; input clk; input [31:0] port_inA_read_rdbuf; input [7:0] port_inA_read_rdlen; input [31:0] port_inA_read_rdaddr; input reset; input clk; reg hprxx10; reg port_inA_netside_rspval; reg port_inA_netside_reop; integer port_inB_read_rxpoi; integer port_outC_read_rxpoi; reg port_outD_netside_eop; reg port_outD_netside_cmdval; reg port_outD_netside_rspack; reg [1:0] eadsubproc10pc; reg [1:0] eadinlined10pc; reg [1:0] eadsubproc11pc; integer port_outD_read_rxpoi; reg [1:0] eadinlined11pc; reg [31:0] port_outD_read_rdbuf; reg [1:0] eadsubproc12pc; integer port_inA_read_rxpoi; reg [1:0] eadinlined12pc; reg [31:0] port_inA_read_rdbuf; reg [31:0] mbuf_A[255:0]; reg [7:0] mlen_A; reg [31:0] maddr_A; reg [2:0] nputdesign10pc; always @(posedge clk) begin //Start Hpr/ls if (reset) port_outD_netside_rspack <= 0; else if (eadsubproc10pc==1 && !port_outD_netside_reop && port_outD_netside_rspval || port_outD_netside_rspval && eadsubproc10pc==2 || eadsubproc10pc==1 && !port_outD_netside_reop && !port_outD_netside_rspval || !port_outD_netside_rspval && eadsubproc10pc==2) port_outD_netside_rspack <= eadsubproc10pc==1 && !port_outD_netside_reop && port_outD_netside_rspval || port_outD_netside_rspval && eadsubproc10pc==2 ? 1: 0; if (reset) port_outD_read_rxpoi <= 0; else if (port_outD_netside_rspval && eadsubproc10pc==1 && !port_outD_netside_reop || !port_outD_netside_rspval && eadsubproc10pc==1 && !port_outD_netside_reop || eadsubproc10pc==1 && port_outD_netside_reop) port_outD_read_rxpoi <= port_outD_read_rxpoi+1; if (reset) mbuf_A[port_outD_read_rxpoi] <= 0; else if (port_outD_netside_rspval && eadsubproc10pc==1 && !port_outD_netside_reop || !port_outD_netside_rspval && eadsubproc10pc==1 && !port_outD_netside_reop || eadsubproc10pc==1 && port_outD_netside_reop) mbuf_A[port_outD_read_rxpoi] <= port_outD_netside_rdata; if (reset) eadsubproc10pc <= 0; else if (eadsubproc10pc==2 && port_outD_netside_rspval) eadsubproc10pc <= 1; if (reset) eadsubproc10pc <= 0; else if (eadsubproc10pc==2 && !port_outD_netside_rspval) eadsubproc10pc <= 2; if (reset) eadsubproc10pc <= 0; else if (eadsubproc10pc==1 && port_outD_netside_reop) eadsubproc10pc <= 2; if (reset) eadsubproc10pc <= 0; else if (eadsubproc10pc==1 && !port_outD_netside_reop && port_outD_netside_rspval) eadsubproc10pc <= 1; if (reset) eadsubproc10pc <= 0; else if (eadsubproc10pc==1 && !port_outD_netside_reop && !port_outD_netside_rspval) eadsubproc10pc <= 2; if (reset) eadsubproc10pc <= 0; else if (eadsubproc10pc==0) eadsubproc10pc <= 2; //End Hpr/ls //Start Hpr/ls if (reset) port_outD_netside_rspack <= 0; else if (!port_outD_netside_reop && eadsubproc11pc==1 && port_outD_netside_rspval || port_outD_netside_rspval && eadsubproc11pc==2 || !port_outD_netside_reop && eadsubproc11pc==1 && !port_outD_netside_rspval || !port_outD_netside_rspval && eadsubproc11pc==2) port_outD_netside_rspack <= !port_outD_netside_reop && eadsubproc11pc==1 && port_outD_netside_rspval || port_outD_netside_rspval && eadsubproc11pc==2 ? 1: 0; if (reset) port_outD_read_rxpoi <= 0; else if (port_outD_netside_rspval && !port_outD_netside_reop && eadsubproc11pc==1 || !port_outD_netside_rspval && !port_outD_netside_reop && eadsubproc11pc==1 || port_outD_netside_reop && eadsubproc11pc==1) port_outD_read_rxpoi <= port_outD_read_rxpoi+1; if (reset) mbuf_A[port_outD_read_rxpoi] <= 0; else if (port_outD_netside_rspval && !port_outD_netside_reop && eadsubproc11pc==1 || !port_outD_netside_rspval && !port_outD_netside_reop && eadsubproc11pc==1 || port_outD_netside_reop && eadsubproc11pc==1) mbuf_A[port_outD_read_rxpoi] <= port_outD_netside_rdata; if (reset) eadsubproc11pc <= 0; else if (eadsubproc11pc==2 && port_outD_netside_rspval) eadsubproc11pc <= 1; if (reset) eadsubproc11pc <= 0; else if (eadsubproc11pc==2 && !port_outD_netside_rspval) eadsubproc11pc <= 2; if (reset) eadsubproc11pc <= 0; else if (eadsubproc11pc==1 && port_outD_netside_reop) eadsubproc11pc <= 2; if (reset) eadsubproc11pc <= 0; else if (eadsubproc11pc==1 && !port_outD_netside_reop && port_outD_netside_rspval) eadsubproc11pc <= 1; if (reset) eadsubproc11pc <= 0; else if (eadsubproc11pc==1 && !port_outD_netside_reop && !port_outD_netside_rspval) eadsubproc11pc <= 2; if (reset) eadsubproc11pc <= 0; else if (eadsubproc11pc==0) eadsubproc11pc <= 2; //End Hpr/ls //Start Hpr/ls if (reset) port_inA_netside_rspval <= 0; else if (eadsubproc12pc==2 && port_inA_netside_rspack || eadsubproc12pc==2 && !port_inA_netside_rspack) port_inA_netside_rspval <= eadsubproc12pc==2 && port_inA_netside_rspack ? 1: 0; if (reset) port_inA_netside_reop <= 0; else if (eadsubproc12pc==1) port_inA_netside_reop <= 1; if (reset) port_inA_read_rxpoi <= 0; else if (eadsubproc12pc==1) port_inA_read_rxpoi <= port_inA_read_rxpoi+1; if (reset) mbuf_A[port_inA_read_rxpoi] <= 0; else if (eadsubproc12pc==1) mbuf_A[port_inA_read_rxpoi] <= port_inA_netside_rdata; if (reset) eadsubproc12pc <= 0; else if (eadsubproc12pc==2 && port_inA_netside_rspack) eadsubproc12pc <= 1; if (reset) eadsubproc12pc <= 0; else if (eadsubproc12pc==2 && !port_inA_netside_rspack) eadsubproc12pc <= 2; if (reset) eadsubproc12pc <= 0; else if (eadsubproc12pc==1) eadsubproc12pc <= 2; if (reset) eadsubproc12pc <= 0; else if (eadsubproc12pc==0) eadsubproc12pc <= 2; //End Hpr/ls end always @(posedge clk) begin //Start Hpr/ls if (reset) port_outD_netside_rspack <= 0; else if (!port_outD_netside_reop && eadinlined10pc==1 && port_outD_netside_rspval || port_outD_netside_rspval && eadinlined10pc==2 || !port_outD_netside_reop && eadinlined10pc==1 && !port_outD_netside_rspval || !port_outD_netside_rspval && eadinlined10pc==2) port_outD_netside_rspack <= !port_outD_netside_reop && eadinlined10pc==1 && port_outD_netside_rspval || port_outD_netside_rspval && eadinlined10pc==2 ? 1: 0; if (reset) port_outD_read_rxpoi <= 0; else if (port_outD_netside_rspval && !port_outD_netside_reop && eadinlined10pc==1 || !port_outD_netside_rspval && !port_outD_netside_reop && eadinlined10pc==1 || port_outD_netside_reop && eadinlined10pc==1) port_outD_read_rxpoi <= port_outD_read_rxpoi+1; if (reset) port_outD_read_rdbuf[port_outD_read_rxpoi] <= 0; else if (port_outD_netside_rspval && !port_outD_netside_reop && eadinlined10pc==1 || !port_outD_netside_rspval && !port_outD_netside_reop && eadinlined10pc==1 || port_outD_netside_reop && eadinlined10pc==1) port_outD_read_rdbuf[port_outD_read_rxpoi] <= port_outD_netside_rdata; if (reset) eadinlined10pc <= 0; else if (eadinlined10pc==2 && port_outD_netside_rspval) eadinlined10pc <= 1; if (reset) eadinlined10pc <= 0; else if (eadinlined10pc==2 && !port_outD_netside_rspval) eadinlined10pc <= 2; if (reset) eadinlined10pc <= 0; else if (eadinlined10pc==1 && port_outD_netside_reop) eadinlined10pc <= 2; if (reset) eadinlined10pc <= 0; else if (eadinlined10pc==1 && !port_outD_netside_reop && port_outD_netside_rspval) eadinlined10pc <= 1; if (reset) eadinlined10pc <= 0; else if (eadinlined10pc==1 && !port_outD_netside_reop && !port_outD_netside_rspval) eadinlined10pc <= 2; if (reset) eadinlined10pc <= 0; else if (eadinlined10pc==0) eadinlined10pc <= 2; //End Hpr/ls //Start Hpr/ls if (reset) port_outD_netside_rspack <= 0; else if (!port_outD_netside_reop && eadinlined11pc==1 && port_outD_netside_rspval || port_outD_netside_rspval && eadinlined11pc==2 || !port_outD_netside_reop && eadinlined11pc==1 && !port_outD_netside_rspval || !port_outD_netside_rspval && eadinlined11pc==2) port_outD_netside_rspack <= !port_outD_netside_reop && eadinlined11pc==1 && port_outD_netside_rspval || port_outD_netside_rspval && eadinlined11pc==2 ? 1: 0; if (reset) port_outD_read_rxpoi <= 0; else if (port_outD_netside_rspval && !port_outD_netside_reop && eadinlined11pc==1 || !port_outD_netside_rspval && !port_outD_netside_reop && eadinlined11pc==1 || port_outD_netside_reop && eadinlined11pc==1) port_outD_read_rxpoi <= port_outD_read_rxpoi+1; if (reset) port_outD_read_rdbuf[port_outD_read_rxpoi] <= 0; else if (port_outD_netside_rspval && !port_outD_netside_reop && eadinlined11pc==1 || !port_outD_netside_rspval && !port_outD_netside_reop && eadinlined11pc==1 || port_outD_netside_reop && eadinlined11pc==1) port_outD_read_rdbuf[port_outD_read_rxpoi] <= port_outD_netside_rdata; if (reset) eadinlined11pc <= 0; else if (eadinlined11pc==2 && port_outD_netside_rspval) eadinlined11pc <= 1; if (reset) eadinlined11pc <= 0; else if (eadinlined11pc==2 && !port_outD_netside_rspval) eadinlined11pc <= 2; if (reset) eadinlined11pc <= 0; else if (eadinlined11pc==1 && port_outD_netside_reop) eadinlined11pc <= 2; if (reset) eadinlined11pc <= 0; else if (eadinlined11pc==1 && !port_outD_netside_reop && port_outD_netside_rspval) eadinlined11pc <= 1; if (reset) eadinlined11pc <= 0; else if (eadinlined11pc==1 && !port_outD_netside_reop && !port_outD_netside_rspval) eadinlined11pc <= 2; if (reset) eadinlined11pc <= 0; else if (eadinlined11pc==0) eadinlined11pc <= 2; //End Hpr/ls //Start Hpr/ls if (reset) port_inA_netside_rspval <= 0; else if (port_inA_netside_rspack && eadinlined12pc==2 || !port_inA_netside_rspack && eadinlined12pc==2) port_inA_netside_rspval <= port_inA_netside_rspack && eadinlined12pc==2 ? 1: 0; if (reset) port_inA_netside_reop <= 0; else if (eadinlined12pc==1) port_inA_netside_reop <= 1; if (reset) port_inA_read_rxpoi <= 0; else if (eadinlined12pc==1) port_inA_read_rxpoi <= port_inA_read_rxpoi+1; if (reset) port_inA_read_rdbuf[port_inA_read_rxpoi] <= 0; else if (eadinlined12pc==1) port_inA_read_rdbuf[port_inA_read_rxpoi] <= port_inA_netside_rdata; if (reset) eadinlined12pc <= 0; else if (eadinlined12pc==2 && port_inA_netside_rspack) eadinlined12pc <= 1; if (reset) eadinlined12pc <= 0; else if (eadinlined12pc==2 && !port_inA_netside_rspack) eadinlined12pc <= 2; if (reset) eadinlined12pc <= 0; else if (eadinlined12pc==1) eadinlined12pc <= 2; if (reset) eadinlined12pc <= 0; else if (eadinlined12pc==0) eadinlined12pc <= 2; //End Hpr/ls //Start Hpr/ls if (reset) port_outD_netside_eop <= 0; else if (nputdesign10pc==1 && 1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && mlen_A-4==0 && mlen_A-4<=7 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 1<=mlen_A && 7<=port_outD_netside_be && port_outD_netside_be<8 || nputdesign10pc==1 && !(1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2) && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && mlen_A-4==0 && mlen_A-4<=7 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 1<=mlen_A && 7 <=port_outD_netside_be && port_outD_netside_be<8 || nputdesign10pc==1 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && mlen_A-4!=0 && mlen_A-4<=7 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 1<=mlen_A && 7<=port_outD_netside_be && port_outD_netside_be<8 || 1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && mlen_A-4==0 && mlen_A-4<=7 && nputdesign10pc==2 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 1<=mlen_A && 7<= port_outD_netside_be && port_outD_netside_be<8 || !(1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2) && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && mlen_A-4==0 && mlen_A-4<=7 && nputdesign10pc==2 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 1<=mlen_A && 7<=port_outD_netside_be && port_outD_netside_be<8 || port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && mlen_A-4!=0 && mlen_A-4<=7 && nputdesign10pc==2 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 1<=mlen_A && 7<= port_outD_netside_be && port_outD_netside_be<8) port_outD_netside_eop <= 1; if (reset) mlen_A <= 0; else if (nputdesign10pc==1 && 1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && mlen_A-4==0 && mlen_A-4<= 7 && 1<=mlen_A || nputdesign10pc==1 && !(1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2) && port_outD_netside_address==maddr_A && port_outD_netside_plen ==mlen_A && port_outD_netside_cmdack && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && mlen_A-4==0 && mlen_A-4<=7 && 1<=mlen_A || nputdesign10pc==1 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && 1<= port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && mlen_A-4!=0 && mlen_A-4<=7 && 1<=mlen_A || 1<= port_inA_netside_cmdval && port_inA_netside_cmdval<2 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && nputdesign10pc==2 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && mlen_A-4==0 && mlen_A-4<=7 && 1 <=mlen_A || !(1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2) && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && nputdesign10pc==2 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && mlen_A-4==0 && mlen_A-4<=7 && 1<=mlen_A || port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && nputdesign10pc==2 && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && mlen_A-4!=0 && mlen_A-4<=7 && 1<=mlen_A || nputdesign10pc==1 && 1<=port_inA_netside_cmdval && port_inA_netside_cmdval<2 && port_outD_netside_address==maddr_A && port_outD_netside_plen==mlen_A && port_outD_netside_cmdack && 1<=port_outD_netside_cmd && port_outD_netside_cmd<2 && 7<=port_outD_netside_be && port_outD_netside_be<8 && 7