kiwi: An example that completes in one clock cycle.

The following program was found in an introductory tutorial on arrays in C#. We compiled it to Verilog with and without the array initialisation data.

Array Odd Number Counting

The following C# code contains no un-unwindable loops and no input data so is nearly all elaborated away at compile time.

This is the C# source code:

// statements_foreach_arrays.cs
// Using foreach with arrays
using System;
class MainClass 
{
   public static void Main() 
   {
      int odd = 0, even = 0;
      int[] arr = new int [] {0,1,2,5,7,8,11};

      foreach (int i in arr) 
      {
         if (i%2 == 0)  
            even++;      
         else 
            odd++;         
      }
      Console.WriteLine("Found {0} Odd Numbers, and {1} Even Numbers.",
                        odd, even) ;
   }
}

The generated CIL .net assembly code was ARRAY.CIL.

The generated Verilog implementation was

module Main(clk, reset);
input clk;
  input reset;
  integer Main_V_6;
  integer Main_V_5;
  integer Main_V_3;
  integer Main_V_1;
  integer Main_V_0;
  reg [31:0] CILAR4873669[6:0];
   always @(posedge clk) begin $display("Found %d Odd Numbers, and %d Even Numbers.", 4, 3);
  
  Main_V_5 <= 7;
  Main_V_0 <= 4;
  Main_V_3 <= 11;
  Main_V_1 <= 3;
  Main_V_6 <= 7;
  CILAR4873669[6] <= 11;
  CILAR4873669[5] <= 8;
  CILAR4873669[4] <= 7;
  CILAR4873669[3] <= 5;
  CILAR4873669[2] <= 2;
  CILAR4873669[1] <= 1;
  CILAR4873669[0] <= 0;
   end 
  endmodule

Alternative Output: Without Array Data

When the array is uninitialised, the tool explores every possible path through the program. Fortunately, there is a finite number of routes, and hence we generate the following (core) output:

  reg [31:0] CILAR4873669[6:0];
  always @(posedge clk) begin 
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 0, 7);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 1, 6);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 2, 5);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 3, 4);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 4, 3);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 5, 2);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 6, 1);
  
  
   if (!(CILAR4873669[6]%2) && !(CILAR4873669[5]%2) && !(CILAR4873669[4]%2) && !(CILAR4873669[3]%2) && !(CILAR4873669[2]%2) && !(CILAR4873669[1]%2) && !(CILAR4873669[0]%2)
        && 1) $display("Found %d Odd Numbers, and %d Even Numbers.", 7, 0);
   end