// CBG Orangepath HPR L/S System // Verilog output file generated at 06/09/2016 15:30:39 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.15t : 30th-August-2016 Unix 3.13.0.65 // /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -vnl-roundtrip=disable -report-each-step -kiwic-finish=enable -kiwic-kcode-dump=enable -kiwic-cil-dump=separately -gtrace-loglevel=0 -firstpass-loglevel=0 -repack-to-roms=disable test55.exe /r:/home/djg11/d320/hprls/kiwipro/kiwic/distro/support/KiwiStringIO.dll -sim 1800 -compose=disable -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test55.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=bblock -repack-to-roms=enable -give-backtrace -report-each-step `timescale 1ns/1ns module DUT(input clk, input reset); integer Ttt50_5_V_1; reg [31:0] test55_f_am_cache0; reg [2:0] xpc10nz; always @(posedge clk ) begin //Start structure HPR /r:/home/djg11/d320/hprls/kiwipro/kiwic/distro/support/KiwiStringIO.dll if (reset) begin Ttt50_5_V_1 <= 32'd0; test55_f_am_cache0 <= 32'd0; xpc10nz <= 3'd0; end else begin case (xpc10nz) 3'sd4/*4:xpc10nz*/: $finish(32'sd0); 3'sd6/*6:xpc10nz*/: begin $display(" %1d %1d baz_topper", 32'sd50+(0-Ttt50_5_V_1), 32'sd1000+Ttt50_5_V_1); $display(" yielding %1d", "kandy"); end endcase if ((Ttt50_5_V_1>=32'sd3) && (xpc10nz==3'sd3/*3:xpc10nz*/)) $display("t55_0 done."); case (xpc10nz) 3'sd0/*0:xpc10nz*/: begin if (!(!test55_f_am_cache0)) begin $display("Kiwi Demo - Test55 starting."); $display("Kiwi Demo - Test55_0 starting - function delegate."); end else begin $display("Kiwi Demo - Test55 starting."); $display("Kiwi Demo - Test55_0 starting - function delegate."); test55_f_am_cache0 <= 32'd0; end xpc10nz <= 3'sd1/*1:xpc10nz*/; end 3'sd2/*2:xpc10nz*/: begin Ttt50_5_V_1 <= 32'sd0; xpc10nz <= 3'sd3/*3:xpc10nz*/; end 3'sd3/*3:xpc10nz*/: if ((Ttt50_5_V_1<32'sd3)) xpc10nz <= 3'sd5/*5:xpc10nz*/; else xpc10nz <= 3'sd4/*4:xpc10nz*/; 3'sd4/*4:xpc10nz*/: xpc10nz <= 3'sd7/*7:xpc10nz*/; 3'sd6/*6:xpc10nz*/: begin Ttt50_5_V_1 <= 32'sd1+Ttt50_5_V_1; xpc10nz <= 3'sd3/*3:xpc10nz*/; end endcase if ((xpc10nz==3'sd1/*1:xpc10nz*/)) xpc10nz <= 3'sd2/*2:xpc10nz*/; if ((xpc10nz==3'sd5/*5:xpc10nz*/)) xpc10nz <= 3'sd6/*6:xpc10nz*/; end //End structure HPR /r:/home/djg11/d320/hprls/kiwipro/kiwic/distro/support/KiwiStringIO.dll end // 1 vectors of width 3 // 1 vectors of width 32 // 32 bits in scalar variables // Total state bits in module = 67 bits. // Total number of leaf cells = 0 endmodule // // LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable //HPR L/S (orangepath) auxiliary reports. //KiwiC compilation report //Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.15t : 30th-August-2016 //06/09/2016 15:30:35 //Cmd line args: /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -vnl-roundtrip=disable -report-each-step -kiwic-finish=enable -kiwic-kcode-dump=enable -kiwic-cil-dump=separately -gtrace-loglevel=0 -firstpass-loglevel=0 -repack-to-roms=disable test55.exe /r:/home/djg11/d320/hprls/kiwipro/kiwic/distro/support/KiwiStringIO.dll -sim 1800 -compose=disable -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test55.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=bblock -repack-to-roms=enable -give-backtrace -report-each-step //---------------------------------------------------------- //Report from KiwiC-fe.rpt::: //KiwiC: front end input processing of class or method called KiwiSystem/Kiwi // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor10 // //KiwiC start_thread (or entry point) id=cctor10 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+0 // //KiwiC: front end input processing of class or method called System/BitConverter // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor12 // //KiwiC start_thread (or entry point) id=cctor12 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+1 // //KiwiC: front end input processing of class or method called KiwiStringIO // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor14 // //KiwiC start_thread (or entry point) id=cctor14 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+2 // //KiwiC: front end input processing of class or method called test55 // //root_compiler: start elaborating class 'test55' // //elaborating class 'test55' // //compiling static method as entry point: style=Root idl=test55/Main // //Performing root elaboration of method Main // //KiwiC start_thread (or entry point) id=Main10 // //root_compiler class done: test55 // //Report of all settings used from the recipe or command line: // // cil-uwind-budget=10000 // // kiwic-finish=enable // // kiwic-cil-dump=separately // // kiwic-kcode-dump=enable // // array-4d-name=KIWIARRAY4D // // array-3d-name=KIWIARRAY3D // // array-2d-name=KIWIARRAY2D // // kiwi-dll=Kiwi.dll // // kiwic-dll=Kiwic.dll // // kiwic-zerolength-arrays=disable // // kiwic-fpgaconsole-default=enable // // postgen-optimise=enable // // gtrace-loglevel=0 // // firstpass-loglevel=0 // // root=$attributeroot // // ?>?=srcfile, test55.exe, /r:/home/djg11/d320/hprls/kiwipro/kiwic/distro/support/KiwiStringIO.dll // //END OF KIWIC REPORT FILE // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // -- No expression aliases to report // //---------------------------------------------------------- //Report from restructure2::: //Offchip Load/Store (and other) Ports = Nothing to Report // //---------------------------------------------------------- //Report from restructure2::: //Restructure Technology Settings //*---------------------------+---------+---------------------------------------------------------------------------------* //| Key | Value | Description | //*---------------------------+---------+---------------------------------------------------------------------------------* //| int_flr_mul | -3000 | | //| fp_fl_dp_div | 5 | | //| fp_fl_dp_add | 4 | | //| fp_fl_dp_mul | 3 | | //| fp_fl_sp_div | 5 | | //| fp_fl_sp_add | 4 | | //| fp_fl_sp_mul | 3 | | //| res2-loadstore-port-count | 0 | | //| max_no_fp_addsubs | 6 | Maximum number of adders and subtractors (or combos) to instantiate per thread. | //| max_no_fp_muls | 6 | Maximum number of f/p multipliers or dividers to instantiate per thread. | //| max_no_int_muls | 3 | Maximum number of int multipliers to instantiate per thread. | //| max_no_fp_divs | 2 | Maximum number of f/p dividers to instantiate per thread. | //| max_no_int_divs | 2 | Maximum number of int dividers to instantiate per thread. | //| res2-offchip-threshold | 1000000 | | //| res2-combrom-threshold | 64 | | //| res2-combram-threshold | 32 | | //| res2-regfile-threshold | 8 | | //*---------------------------+---------+---------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for xpc10 //*------------------+-----+-------------+------+------+-------+-----+-------------+--------* //| gb-flag/Pause | eno | hwm | root | exec | start | end | antecedants | next | //*------------------+-----+-------------+------+------+-------+-----+-------------+--------* //| X0:"0:xpc10" | 901 | hwm=0.0.0 | 0 | 0 | - | - | --- | 1 | //| X0:"0:xpc10" | 900 | hwm=0.0.0 | 0 | 0 | - | - | --- | 1 | //| X1:"1:xpc10" | 902 | hwm=0.0.0 | 1 | 1 | - | - | --- | 2 | //| X2:"2:xpc10" | 903 | hwm=0.0.0 | 2 | 2 | - | - | --- | 3 | //| X4:"4:xpc10" | 905 | hwm=0.0.0 | 3 | 3 | - | - | --- | 4 | //| X4:"4:xpc10" | 904 | hwm=0.0.0 | 3 | 3 | - | - | --- | 5 | //| X8:"8:xpc10" | 906 | hwm=0.0.0 | 4 | 4 | - | - | --- | <NONE> | //| X16:"16:xpc10" | 907 | hwm=0.0.0 | 5 | 5 | - | - | --- | 6 | //| X32:"32:xpc10" | 908 | hwm=0.0.0 | 6 | 6 | - | - | --- | 3 | //*------------------+-----+-------------+------+------+-------+-----+-------------+--------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"0:xpc10" 901 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"0:xpc10" 900 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X0:"0:xpc10" //res2: Thread=xpc10 state=X0:"0:xpc10" //*-----+-----+---------+-------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-------------------------------------------------------------------------------------------------------------* //| 0 | - | R0 CTRL | | //| 0 | 900 | R0 DATA | | //| 0+E | 900 | W0 DATA | PLI:Kiwi Demo - Test55_0... PLI:Kiwi Demo - Test55 s... | //| 0 | 901 | R0 DATA | | //| 0+E | 901 | W0 DATA | test55_<>f__am$cache0 te=te:0 scalarw({SC:d29,0}) PLI:Kiwi Demo - Test55_0... PLI:Kiwi Demo - Test55 s... | //*-----+-----+---------+-------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1:"1:xpc10" 902 : major_start_pcl=1 edge_private_start/end=-1/-1 exec=1 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1:"1:xpc10" //res2: Thread=xpc10 state=X1:"1:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 1 | - | R0 CTRL | | //| 1 | 902 | R0 DATA | | //| 1+E | 902 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"2:xpc10" 903 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X2:"2:xpc10" //res2: Thread=xpc10 state=X2:"2:xpc10" //*-----+-----+---------+--------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+--------------------------------* //| 2 | - | R0 CTRL | | //| 2 | 903 | R0 DATA | | //| 2+E | 903 | W0 DATA | Ttt50.5_V_1 te=te:2 scalarw(0) | //*-----+-----+---------+--------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"4:xpc10" 905 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"4:xpc10" 904 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X4:"4:xpc10" //res2: Thread=xpc10 state=X4:"4:xpc10" //*-----+-----+---------+------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------------------* //| 3 | - | R0 CTRL | | //| 3 | 904 | R0 DATA | | //| 3+E | 904 | W0 DATA | | //| 3 | 905 | R0 DATA | | //| 3+E | 905 | W0 DATA | PLI:t55_0 done. | //*-----+-----+---------+------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 906 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X8:"8:xpc10" //res2: Thread=xpc10 state=X8:"8:xpc10" //*-----+-----+---------+-----------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------* //| 4 | - | R0 CTRL | | //| 4 | 906 | R0 DATA | | //| 4+E | 906 | W0 DATA | PLI:GSAI:hpr_sysexit | //*-----+-----+---------+-----------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 907 : major_start_pcl=5 edge_private_start/end=-1/-1 exec=5 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X16:"16:xpc10" //res2: Thread=xpc10 state=X16:"16:xpc10" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 5 | - | R0 CTRL | | //| 5 | 907 | R0 DATA | | //| 5+E | 907 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"32:xpc10" 908 : major_start_pcl=6 edge_private_start/end=-1/-1 exec=6 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32:"32:xpc10" //res2: Thread=xpc10 state=X32:"32:xpc10" //*-----+-----+---------+---------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+---------------------------------------------------------------------------------------* //| 6 | - | R0 CTRL | | //| 6 | 908 | R0 DATA | | //| 6+E | 908 | W0 DATA | Ttt50.5_V_1 te=te:6 scalarw(1+Ttt50.5_V_1) PLI: yielding %d PLI: %u %u baz_topper | //*-----+-----+---------+---------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // -- No expression aliases to report // //---------------------------------------------------------- //Report from verilog_render::: //1 vectors of width 3 // //1 vectors of width 32 // //32 bits in scalar variables // //Total state bits in module = 67 bits. // //Total number of leaf cells = 0 // //Major Statistics Report: //Thread .cctor uid=cctor10 has 3 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor12 has 2 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor14 has 5 CIL instructions in 1 basic blocks //Thread Main uid=Main10 has 26 CIL instructions in 6 basic blocks //Thread Main uid=Main10 has 33 CIL instructions in 7 basic blocks //Thread mpc10 has 7 bevelab control states (pauses) //Reindexed thread xpc10 with 7 minor control states // eof (HPR L/S Verilog)