H2 Language Example: Primes

Primes Demonstration in H2

A standard test for a programming language is to print out a list of prime numbers using the sieve method. This sheet gives the source code for a primes test using the C-like subset of the H2 language.

Source Code

// $Id :
// A basic H2 test: print the primes up to 50.
//
interface PRIMES()
{
  const limit = 50;
  node [15:0]: i, j, k;
  node  [3:0] [1000]: PA;
  {
     printf("Primes test %i starting\n", tnow);
     for (i = 0; i<limit; i +=1)
	{
	  wait(1);
	  PA[i] = 1;
	}
        j = 2;
	wait(1);
	printf("Primes test: cleared array at tnow=%i \n", tnow);
	while (j<limit)
	{
	  i=j+j;
	  wait(1);
	  //printf(" j=%i  i=%i j=%i start\n", j, i, j);
	  while (i<limit) { PA[i] = 0; i += j; 	wait(1); }
	  j += 1;
	}
	printf("The primes are:");
	wait(1);
	for(i=1; i<limit; i += 1) { if (PA[i]) printf("%i ", i); wait(1); }
	wait(1);
	printf("\n");
     printf("Primes test: complete at tnow=%i.\n", tnow);
     sysexit(0);
  }
} 
// eof

Object Code: H2 VM

The virtual machine code generated is primes_vm. The number of VM instructions used is 41.

Running this code results in the following output

  ./h2comp testsrc/basictests.h2 -sim 15000 -root PRIMES
  Primes test 1 starting
  Primes test: cleared array at tnow=308 
  The primes are:1 2 3 5 7 11 13 17 19 23 29 31 37 41 43 47 
  Primes test: complete at tnow=1735.
  h2comp done

Object Code: Micro-controller code

The microcode assembly language generated is primes.s. This uses 240 memory locations on the micro-controller.

The microcode ISA and assembly language was defined by this spec file microcode_hdr.sml.

Running this code results in the following output

./h2comp testsrc/basictests.h2 -sim 15000 -root PRIMES -ucode 10 -sim-ucode 1
Primes test *UNDEF starting
Primes test: cleared array at tnow=2 
The primes are:1 2 3 5 7 11 13 17 19 23 29 31 37 41 43 47 
Primes test: complete at tnow=1899.
Simulation natural end at 1899
h2comp done

Object Code: Verilog

The Verilog RTL design generated is primes.v.

The Verilog RTL was also output as a gate-level design primes.vnl.

Running this code results in the following output

Object Code: SystemC

The SystemC output code generated is primes.cpp and primes.h. Note July 2024: SystemC files are seemingly missing.