// CBG Orangepath HPR L/S System

// Verilog output file generated at 07/01/2016 13:41:37
// Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 57a: November-2015 Unix 3.19.8.100
//  /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -verilog-roundtrip=disable -report-each-step -kiwic-finish=enable -kiwic-cil-dump=separately test39.exe -sim 1800 -vnl-resets=synchronous -vnl DUT.v -give-backtrace -report-each-step
`timescale 1ns/10ps


module DUT(    output hf1_dram0bank_opreq,
    input hf1_dram0bank_oprdy,
    input hf1_dram0bank_ack,
    output hf1_dram0bank_rwbar,
    output [255:0] hf1_dram0bank_wdata,
    output [21:0] hf1_dram0bank_addr,
    input [255:0] hf1_dram0bank_rdata,
    output [31:0] hf1_dram0bank_lanes,
    input clk,
    input reset);
  reg [31:0] tTMT4Main_V_0;
  integer tTMT4Main_V_1;
  reg [31:0] tTMT4Main_V_2;
  reg [31:0] tTMT4Main_V_3;
  reg [31:0] Ttby1_6_V_0;
  reg [31:0] test39_byte_list_pair_freelist;
  reg [31:0] A_sListPair_1_8_US_T1_CC_MAPR10NoCE0_cdr;
  reg [31:0] A_sListPair_1_8_US_T1_CC_MAPR10NoCE1_cdr;
  reg [31:0] A_sListPair_1_8_US_T1_CC_MAPR10NoCE2_cdr;
  reg [31:0] A_sListPair_1_8_US_T1_CC_MAPR10NoCE3_cdr;
  reg [7:0] A_8_US_CC_MAPR10NoCE0_car;
  reg [7:0] A_8_US_CC_MAPR10NoCE1_car;
  reg [7:0] A_8_US_CC_MAPR10NoCE2_car;
  reg [7:0] A_8_US_CC_MAPR10NoCE3_car;
  reg [4:0] xpc10nz;
  wire [31:0] hprpin25210;
 always   @(posedge clk )  begin 
      //Start structure HPR test39.exe
      if (reset)  begin 
               Ttby1_6_V_0 <= 32'd0;
               tTMT4Main_V_3 <= 32'd0;
               tTMT4Main_V_2 <= 32'd0;
               tTMT4Main_V_0 <= 32'd0;
               tTMT4Main_V_1 <= 32'd0;
               A_8_US_CC_MAPR10NoCE0_car <= 8'd0;
               A_sListPair_1_8_US_T1_CC_MAPR10NoCE0_cdr <= 32'd0;
               A_8_US_CC_MAPR10NoCE1_car <= 8'd0;
               A_sListPair_1_8_US_T1_CC_MAPR10NoCE1_cdr <= 32'd0;
               A_8_US_CC_MAPR10NoCE2_car <= 8'd0;
               A_sListPair_1_8_US_T1_CC_MAPR10NoCE2_cdr <= 32'd0;
               A_8_US_CC_MAPR10NoCE3_car <= 8'd0;
               A_sListPair_1_8_US_T1_CC_MAPR10NoCE3_cdr <= 32'd0;
               test39_byte_list_pair_freelist <= 32'd0;
               xpc10nz <= 5'd0;
               end 
               else  begin 
              if ((tTMT4Main_V_1<2'd3) && !test39_byte_list_pair_freelist && (xpc10nz==5'd19/*19:US*/)) $display("  Kiwi RunTimeAbend  msg=%d code=%d"
                  , "no free cells", 1'd1);
                  if (!tTMT4Main_V_3 && (xpc10nz==5'd18/*18:US*/))  begin 
                      $display("Test 39 Linked List Simple Demo Finished.");
                      $finish(0);
                       end 
                      
              case (xpc10nz)

              0/*0:US*/:  begin 
                  $display("Test 39 Linked List Simple Demo.  Poolsize=%d", 4);
                  $display("  Created Item %d", 33'h1ffffffff&32'd0);
                  $display("  Created Item %d", 33'h1ffffffff&32'd1);
                  $display("  Created Item %d", 33'h1ffffffff&32'd2);
                  $display("  Created Item %d", 33'h1ffffffff&32'd3);
                  $display("Test 39: Freepool created.");
                  $display("Test 39 Linked List Simple Demo.");
                   A_8_US_CC_MAPR10NoCE0_car <= 9'h1ff&8'd0;
                   A_sListPair_1_8_US_T1_CC_MAPR10NoCE0_cdr <= test39_byte_list_pair_freelist;
                   A_8_US_CC_MAPR10NoCE1_car <= 9'h1ff&8'd11;
                   A_sListPair_1_8_US_T1_CC_MAPR10NoCE1_cdr <= 32'd0;
                   A_8_US_CC_MAPR10NoCE2_car <= 9'h1ff&8'd22;
                   A_sListPair_1_8_US_T1_CC_MAPR10NoCE2_cdr <= 32'd1;
                   A_8_US_CC_MAPR10NoCE3_car <= 9'h1ff&8'd33;
                   A_sListPair_1_8_US_T1_CC_MAPR10NoCE3_cdr <= 32'd2;
                   test39_byte_list_pair_freelist <= 32'd3;
                   xpc10nz <= 5'd20/*20:xpc10nz*/;
                   end 
                  
              3'd7/*7:US*/: $display("  Runtime Alloc Item %d", tTMT4Main_V_1);

              5'd16/*16:US*/: $display("  Readback Item %d", ((tTMT4Main_V_3==2'd3/*3:US*/)? A_8_US_CC_MAPR10NoCE3_car: ((tTMT4Main_V_3
              ==2'd2/*2:US*/)? A_8_US_CC_MAPR10NoCE2_car: ((tTMT4Main_V_3==1'd1/*1:US*/)? A_8_US_CC_MAPR10NoCE1_car: ((tTMT4Main_V_3==
              0/*0:US*/)? A_8_US_CC_MAPR10NoCE0_car: 1'bx)))));

              5'd19/*19:US*/:  begin 
                  if ((tTMT4Main_V_1<2'd3) && !(!test39_byte_list_pair_freelist) && (test39_byte_list_pair_freelist==2'd3/*3:US*/))  begin 
                           Ttby1_6_V_0 <= test39_byte_list_pair_freelist;
                           A_8_US_CC_MAPR10NoCE3_car <= 9'h1ff&8'd50+8'd3*tTMT4Main_V_1;
                           test39_byte_list_pair_freelist <= hprpin25210;
                           xpc10nz <= 3'd6/*6:xpc10nz*/;
                           end 
                          if ((tTMT4Main_V_1<2'd3) && !(!test39_byte_list_pair_freelist) && (test39_byte_list_pair_freelist!=2'd3/*3:US*/)) 
                           begin 
                           Ttby1_6_V_0 <= test39_byte_list_pair_freelist;
                           test39_byte_list_pair_freelist <= hprpin25210;
                           xpc10nz <= 3'd5/*5:xpc10nz*/;
                           end 
                          if ((tTMT4Main_V_1<2'd3) && !test39_byte_list_pair_freelist)  begin 
                           Ttby1_6_V_0 <= 33'h1ffffffff&32'd0;
                           xpc10nz <= 4'd15/*15:xpc10nz*/;
                           end 
                          if ((tTMT4Main_V_1>=2'd3))  begin 
                           tTMT4Main_V_3 <= tTMT4Main_V_0;
                           xpc10nz <= 5'd18/*18:xpc10nz*/;
                           end 
                           end 
                  endcase
              if ((Ttby1_6_V_0==2'd3/*3:US*/))  begin if ((xpc10nz==4'd15/*15:US*/))  begin 
                           tTMT4Main_V_2 <= Ttby1_6_V_0;
                           A_sListPair_1_8_US_T1_CC_MAPR10NoCE3_cdr <= tTMT4Main_V_0;
                           xpc10nz <= 4'd14/*14:xpc10nz*/;
                           end 
                           end 
                   else if ((xpc10nz==4'd15/*15:US*/))  begin 
                           tTMT4Main_V_2 <= Ttby1_6_V_0;
                           xpc10nz <= 4'd13/*13:xpc10nz*/;
                           end 
                          
              case (xpc10nz)

              3'd7/*7:US*/:  begin 
                   tTMT4Main_V_0 <= tTMT4Main_V_2;
                   tTMT4Main_V_1 <= 33'h1ffffffff&32'd1+tTMT4Main_V_1;
                   xpc10nz <= 5'd19/*19:xpc10nz*/;
                   end 
                  
              5'd18/*18:US*/: if (!(!tTMT4Main_V_3))  xpc10nz <= 5'd17/*17:xpc10nz*/;
                   else  xpc10nz <= 5'd18/*18:xpc10nz*/;
              endcase
              if ((Ttby1_6_V_0==1'd1/*1:US*/))  begin if ((xpc10nz==2'd3/*3:US*/))  begin 
                           A_8_US_CC_MAPR10NoCE1_car <= 9'h1ff&8'd50+8'd3*tTMT4Main_V_1;
                           xpc10nz <= 2'd2/*2:xpc10nz*/;
                           end 
                           end 
                   else if ((xpc10nz==2'd3/*3:US*/))  xpc10nz <= 1'd1/*1:xpc10nz*/;
                      if ((Ttby1_6_V_0==2'd2/*2:US*/))  begin if ((xpc10nz==3'd5/*5:US*/))  begin 
                           A_8_US_CC_MAPR10NoCE2_car <= 9'h1ff&8'd50+8'd3*tTMT4Main_V_1;
                           xpc10nz <= 3'd4/*4:xpc10nz*/;
                           end 
                           end 
                   else if ((xpc10nz==3'd5/*5:US*/))  xpc10nz <= 2'd3/*3:xpc10nz*/;
                      if ((0==tTMT4Main_V_2))  begin if ((xpc10nz==4'd9/*9:US*/))  begin 
                           A_sListPair_1_8_US_T1_CC_MAPR10NoCE0_cdr <= tTMT4Main_V_0;
                           xpc10nz <= 4'd8/*8:xpc10nz*/;
                           end 
                           end 
                   else if ((xpc10nz==4'd9/*9:US*/))  xpc10nz <= 3'd7/*7:xpc10nz*/;
                      if ((1'd1==tTMT4Main_V_2))  begin if ((xpc10nz==4'd11/*11:US*/))  begin 
                           A_sListPair_1_8_US_T1_CC_MAPR10NoCE1_cdr <= tTMT4Main_V_0;
                           xpc10nz <= 4'd10/*10:xpc10nz*/;
                           end 
                           end 
                   else if ((xpc10nz==4'd11/*11:US*/))  xpc10nz <= 4'd9/*9:xpc10nz*/;
                      if ((tTMT4Main_V_2==2'd2/*2:US*/))  begin if ((xpc10nz==4'd13/*13:US*/))  begin 
                           A_sListPair_1_8_US_T1_CC_MAPR10NoCE2_cdr <= tTMT4Main_V_0;
                           xpc10nz <= 4'd12/*12:xpc10nz*/;
                           end 
                           end 
                   else if ((xpc10nz==4'd13/*13:US*/))  xpc10nz <= 4'd11/*11:xpc10nz*/;
                      
              case (xpc10nz)

              1'd1/*1:US*/:  begin 
                  if ((Ttby1_6_V_0==0/*0:US*/))  A_8_US_CC_MAPR10NoCE0_car <= 9'h1ff&8'd50+8'd3*tTMT4Main_V_1;
                       xpc10nz <= 4'd15/*15:xpc10nz*/;
                   end 
                  
              5'd16/*16:US*/:  begin 
                   tTMT4Main_V_3 <= ((tTMT4Main_V_3==2'd3/*3:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE3_cdr: ((tTMT4Main_V_3==2'd2/*2:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE2_cdr
                  : ((tTMT4Main_V_3==1'd1/*1:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE1_cdr: ((tTMT4Main_V_3==0/*0:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE0_cdr
                  : 32'bx))));

                   xpc10nz <= 5'd18/*18:xpc10nz*/;
                   end 
                  
              5'd20/*20:US*/:  begin 
                   tTMT4Main_V_0 <= 33'h1ffffffff&32'd0;
                   tTMT4Main_V_1 <= 33'h1ffffffff&32'd0;
                   xpc10nz <= 5'd19/*19:xpc10nz*/;
                   end 
                  endcase
              if ((xpc10nz==2'd2/*2:US*/))  xpc10nz <= 1'd1/*1:xpc10nz*/;
                  if ((xpc10nz==3'd4/*4:US*/))  xpc10nz <= 2'd3/*3:xpc10nz*/;
                  if ((xpc10nz==3'd6/*6:US*/))  xpc10nz <= 3'd5/*5:xpc10nz*/;
                  if ((xpc10nz==4'd8/*8:US*/))  xpc10nz <= 3'd7/*7:xpc10nz*/;
                  if ((xpc10nz==4'd10/*10:US*/))  xpc10nz <= 4'd9/*9:xpc10nz*/;
                  if ((xpc10nz==4'd12/*12:US*/))  xpc10nz <= 4'd11/*11:xpc10nz*/;
                  if ((xpc10nz==4'd14/*14:US*/))  xpc10nz <= 4'd13/*13:xpc10nz*/;
                  if ((xpc10nz==5'd17/*17:US*/))  xpc10nz <= 5'd16/*16:xpc10nz*/;
                   end 
              //End structure HPR test39.exe


       end 
      

assign hprpin25210 = ((test39_byte_list_pair_freelist==2'd3/*3:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE3_cdr: ((test39_byte_list_pair_freelist==2'd2/*2:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE2_cdr
: ((test39_byte_list_pair_freelist==1'd1/*1:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE1_cdr: ((test39_byte_list_pair_freelist==0/*0:US*/)? A_sListPair_1_8_US_T1_CC_MAPR10NoCE0_cdr
: 32'bx))));

//Total area 0
// 1 vectors of width 5
// 4 vectors of width 8
// 9 vectors of width 32
// 32 bits in scalar variables
// Total state bits in module = 357 bits.
// 32 continuously assigned (wire/non-state) bits 
// Total number of leaf cells = 0
endmodule

// 
/*

// Highest off-chip SRAM/DRAM location in use on port dram0bank is <null> (--not-used--) bytes=1048576
// Offchip Memory Physical Ports/Banks
*-----------+----------+----------+--------+--------+-------+-----------*
| Name      | Protocol | No Words | Awidth | Dwidth | Lanes | LaneWidth |
*-----------+----------+----------+--------+--------+-------+-----------*
| dram0bank | HFAST1   | 4194304  | 22     | 256    | 32    | 8         |
*-----------+----------+----------+--------+--------+-------+-----------*

// */

//  
// LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable
// eof (HPR L/S Verilog)