// CBG Orangepath HPR L/S System // Verilog output file generated at 30/05/2016 08:23:14 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.14 : 29-May-2016 Linux/X86_64:koo // Z:\home\djg11\d320\hprls\kiwipro\kiwic\distro\lib\kiwic.exe -vnl-roundtrip=disable -report-each-step -kiwic-finish=enable -res2-pipelining=off -kiwic-cil-dump=separately test50.exe -sim 1800 -compose=disable -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test50.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=soft -give-backtrace -report-each-step `timescale 1ns/1ns module DUT(input clk, input reset); reg test50_exiting; reg signed [31:0] test50_sum; reg signed [15:0] test50_command2; integer Ttte0_12_V_0; integer Ttcl0_12_V_0; integer Ttcl0_12_V_1; integer Ttcl25_3_V_0; integer Ttcl25_3_V_1; integer tTsT4secondProcess_V_0; integer tTsT4secondProcess_V_1; integer tTsT4secondProcess_V_2; wire [31:0] A_SINT_CC_SCALbx10_ARA0_RDD0; reg [4:0] A_SINT_CC_SCALbx10_ARA0_AD0; reg A_SINT_CC_SCALbx10_ARA0_WEN0; reg A_SINT_CC_SCALbx10_ARA0_REN0; reg [31:0] A_SINT_CC_SCALbx10_ARA0_WRD0; wire [31:0] A_SINT_CC_SCALbx10_ARA0_RDD1; reg [4:0] A_SINT_CC_SCALbx10_ARA0_AD1; reg A_SINT_CC_SCALbx10_ARA0_WEN1; wire A_SINT_CC_SCALbx10_ARA0_REN1; reg [31:0] A_SINT_CC_SCALbx10_ARA0_WRD1; reg [4:0] xpc12nz; reg signed [31:0] SINTCCSCALbx10ARA0RRh10hold; reg SINTCCSCALbx10ARA0RRh10shot0; reg [5:0] xpc10nz; always @(* ) begin A_SINT_CC_SCALbx10_ARA0_WRD0 = 0; A_SINT_CC_SCALbx10_ARA0_AD0 = 0; A_SINT_CC_SCALbx10_ARA0_REN0 = 0; A_SINT_CC_SCALbx10_ARA0_WEN0 = 0; A_SINT_CC_SCALbx10_ARA0_AD1 = 0; A_SINT_CC_SCALbx10_ARA0_WRD1 = 0; A_SINT_CC_SCALbx10_ARA0_WEN1 = 0; A_SINT_CC_SCALbx10_ARA0_WEN1 = (Ttcl25_3_V_1<5'd29) && (xpc10nz==5'd17/*US*/) || (xpc10nz==3'd5/*US*/) || (xpc10nz==1'd1/*US*/) || (Ttcl0_12_V_1<5'd29) && (xpc10nz==2'd3/*US*/) || (xpc10nz==5'd19/*US*/) || ((xpc10nz==5'd23/*US*/) || (xpc10nz==4'd15/*US*/)) && (test50_command2==7'd73/*US*/); if ((xpc10nz==1'd1/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = 32'h1e; A_SINT_CC_SCALbx10_ARA0_AD1 = 5'd0; end if ((Ttcl0_12_V_1<5'd29) && (xpc10nz==2'd3/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = Ttcl0_12_V_0; A_SINT_CC_SCALbx10_ARA0_AD1 = 32'd1+Ttcl0_12_V_1; end if ((xpc10nz==3'd5/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = 32'd99; A_SINT_CC_SCALbx10_ARA0_AD1 = 5'd29; end if ((test50_command2==7'd73/*US*/) && (xpc10nz==4'd15/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = 32'd40+Ttte0_12_V_0; A_SINT_CC_SCALbx10_ARA0_AD1 = 5'd0; end if ((Ttcl25_3_V_1<5'd29) && (xpc10nz==5'd17/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = Ttcl25_3_V_0; A_SINT_CC_SCALbx10_ARA0_AD1 = 32'd1+Ttcl25_3_V_1; end if ((xpc10nz==5'd19/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = 32'd99; A_SINT_CC_SCALbx10_ARA0_AD1 = 5'd29; end if ((test50_command2==7'd73/*US*/) && (xpc10nz==5'd23/*US*/)) begin A_SINT_CC_SCALbx10_ARA0_WRD1 = 32'd40+Ttte0_12_V_0; A_SINT_CC_SCALbx10_ARA0_AD1 = 5'd0; end A_SINT_CC_SCALbx10_ARA0_WEN0 = (xpc12nz==3'd4/*US*/); A_SINT_CC_SCALbx10_ARA0_REN0 = (test50_exiting? (xpc12nz==4'd12/*US*/) && (tTsT4secondProcess_V_1>=5'd29): (xpc12nz==4'd10/*US*/) && (tTsT4secondProcess_V_1>=5'd29) || (xpc12nz==0/*US*/) && (test50_command2==7'd68/*US*/)) || (tTsT4secondProcess_V_2<5'd29) && (xpc12nz ==4'd15/*US*/) || (xpc12nz==2'd2/*US*/) && (test50_command2==7'd68/*US*/) || (xpc12nz==4'd8/*US*/) && (tTsT4secondProcess_V_1<5'd29 ); if ((xpc12nz==0/*US*/)) begin if (!test50_exiting && (test50_command2==7'd68/*US*/)) A_SINT_CC_SCALbx10_ARA0_AD0 = 5'd0; end if ((xpc12nz==2'd2/*US*/)) begin if ((test50_command2==7'd68/*US*/)) A_SINT_CC_SCALbx10_ARA0_AD0 = 5'd0; end if ((xpc12nz==3'd4/*US*/)) begin if (test50_exiting && (tTsT4secondProcess_V_0>=5'd29)) begin A_SINT_CC_SCALbx10_ARA0_WRD0 = test50_sum+tTsT4secondProcess_V_0; A_SINT_CC_SCALbx10_ARA0_AD0 = tTsT4secondProcess_V_0; end if (!test50_exiting && (tTsT4secondProcess_V_0>=5'd29)) begin A_SINT_CC_SCALbx10_ARA0_WRD0 = test50_sum+tTsT4secondProcess_V_0; A_SINT_CC_SCALbx10_ARA0_AD0 = tTsT4secondProcess_V_0; end if ((tTsT4secondProcess_V_0<5'd29)) begin A_SINT_CC_SCALbx10_ARA0_WRD0 = test50_sum+tTsT4secondProcess_V_0; A_SINT_CC_SCALbx10_ARA0_AD0 = tTsT4secondProcess_V_0; end end if ((xpc12nz==4'd12/*US*/)) begin if (test50_exiting && (tTsT4secondProcess_V_1>=5'd29)) A_SINT_CC_SCALbx10_ARA0_AD0 = tTsT4secondProcess_V_1 ; end if ((xpc12nz==4'd10/*US*/)) begin if (!test50_exiting && (tTsT4secondProcess_V_1>=5'd29)) A_SINT_CC_SCALbx10_ARA0_AD0 = tTsT4secondProcess_V_1 ; end if ((tTsT4secondProcess_V_1<5'd29)) begin if ((xpc12nz==4'd8/*US*/)) A_SINT_CC_SCALbx10_ARA0_AD0 = tTsT4secondProcess_V_1 ; end if ((tTsT4secondProcess_V_2<5'd29)) begin if ((xpc12nz==4'd15/*US*/)) A_SINT_CC_SCALbx10_ARA0_AD0 = 1'd1+tTsT4secondProcess_V_2 ; end end always @(posedge clk ) begin //Start structure HPR test50.exe if (reset) begin tTsT4secondProcess_V_2 <= 32'd0; tTsT4secondProcess_V_1 <= 32'd0; tTsT4secondProcess_V_0 <= 32'd0; xpc12nz <= 5'd0; Ttcl25_3_V_1 <= 32'd0; Ttcl25_3_V_0 <= 32'd0; Ttte0_12_V_0 <= 32'd0; Ttcl0_12_V_1 <= 32'd0; Ttcl0_12_V_0 <= 32'd0; test50_exiting <= 1'd0; test50_sum <= 32'd0; test50_command2 <= 16'd0; SINTCCSCALbx10ARA0RRh10hold <= 32'd0; SINTCCSCALbx10ARA0RRh10shot0 <= 1'd0; xpc10nz <= 6'd0; end else begin if ((tTsT4secondProcess_V_2<5'd29) && (xpc12nz==5'd16/*US*/)) $display("sp: Print data: sharedData[%1d] = %1d", 1'd1+tTsT4secondProcess_V_2 , ((xpc12nz==5'd16/*US*/)? A_SINT_CC_SCALbx10_ARA0_RDD0: SINTCCSCALbx10ARA0RRh10hold)); if (test50_exiting && (tTsT4secondProcess_V_2>=5'd29) && (xpc12nz==4'd15/*US*/)) $finish(0); if (test50_exiting && (xpc12nz==4'd14/*US*/)) $finish(0); if (test50_exiting && (tTsT4secondProcess_V_1>=5'd29) && (xpc12nz==4'd13/*US*/)) $finish(0); if (test50_exiting && (tTsT4secondProcess_V_0>=5'd29) && (xpc12nz==3'd4/*US*/)) $finish(0); if ((test50_command2!=7'd73/*US*/) && test50_exiting && (test50_command2!=7'd85/*US*/) && (test50_command2!=7'd83/*US*/) && (test50_command2!=7'd80/*US*/) && (test50_command2!=7'd68/*US*/) && (xpc12nz==2'd2/*US*/)) $finish(0); if ((test50_command2==7'd68/*US*/) && (xpc12nz==2'd3/*US*/)) $display("sp: Print data: sharedData[%1d] = %1d", 0, ((xpc12nz ==2'd3/*US*/)? A_SINT_CC_SCALbx10_ARA0_RDD0: SINTCCSCALbx10ARA0RRh10hold)); if ((xpc12nz==2'd2/*US*/)) begin if ((test50_command2==7'd80/*US*/)) $display("sp: data sum %1d", test50_sum); if ((test50_command2==7'd73/*US*/) && test50_exiting) $finish(0); end if (!test50_exiting && (test50_command2==7'd68/*US*/) && (xpc12nz==1'd1/*US*/)) $display("sp: Print data: sharedData[%1d] = %1d" , 0, ((xpc12nz==1'd1/*US*/)? A_SINT_CC_SCALbx10_ARA0_RDD0: SINTCCSCALbx10ARA0RRh10hold)); if ((xpc12nz==0/*US*/)) begin if (!test50_exiting && (test50_command2==7'd80/*US*/)) $display("sp: data sum %1d", test50_sum); if (test50_exiting) $finish(0); end if ((test50_command2==7'd73/*US*/) && (xpc10nz==5'd30/*US*/)) $display(" Test50 fancy=%1d rs=%c sum=%1d.", 0, test50_command2 , test50_sum); case (xpc10nz) 5'd21/*US*/: $display(" point2 %c %1d.", test50_command2, test50_sum); 5'd22/*US*/: if ((Ttte0_12_V_0<2'd2)) $display(" Test50 fancy=%1d rs=%c sum=%1d.", 1'd1+Ttte0_12_V_0, test50_command2 , test50_sum); else begin $display("Finished main process."); $display("Test50 starting join."); $display("Test50 done."); $finish(0); end endcase if ((test50_command2==7'd73/*US*/) && (xpc10nz==4'd9/*US*/)) $display(" Test50 fancy=%1d rs=%c sum=%1d.", 0, test50_command2 , test50_sum); case (xpc10nz) 0/*US*/: $display("Kiwi Demo - Test50 starting."); 1'd1/*US*/: begin $display("Kiwi Demo - Test50 phase0 starting."); $display(" Test50 Remote Status=%c, sum= %1d", test50_command2, test50_sum); end endcase if ((test50_command2==7'd73/*US*/)) case (xpc10nz) 4'd8/*US*/: begin test50_command2 <= 16'h44; xpc10nz <= 4'd9/*xpc10nz*/; end 4'd9/*US*/: begin Ttte0_12_V_0 <= 32'd0; test50_command2 <= 16'h50; xpc10nz <= 4'd10/*xpc10nz*/; end 4'd10/*US*/: begin test50_command2 <= 16'h53; xpc10nz <= 4'd11/*xpc10nz*/; end 4'd11/*US*/: begin test50_command2 <= 16'h50; xpc10nz <= 4'd12/*xpc10nz*/; end 4'd12/*US*/: begin test50_command2 <= 16'h55; xpc10nz <= 4'd13/*xpc10nz*/; end 4'd13/*US*/: begin test50_command2 <= 16'h53; xpc10nz <= 4'd14/*xpc10nz*/; end 4'd14/*US*/: begin test50_command2 <= 16'h50; xpc10nz <= 4'd15/*xpc10nz*/; end 4'd15/*US*/: begin Ttcl25_3_V_1 <= 32'd0; Ttcl25_3_V_0 <= 32'd1+(32'hffffffff&32'd40+Ttte0_12_V_0); xpc10nz <= 5'd16/*xpc10nz*/; end 5'd23/*US*/: begin Ttcl25_3_V_1 <= 32'd0; Ttcl25_3_V_0 <= 32'd1+(32'hffffffff&32'd40+Ttte0_12_V_0); xpc10nz <= 5'd24/*xpc10nz*/; end 5'd25/*US*/: begin test50_command2 <= 16'h50; xpc10nz <= 4'd15/*xpc10nz*/; end 5'd26/*US*/: begin test50_command2 <= 16'h53; xpc10nz <= 4'd14/*xpc10nz*/; end 5'd27/*US*/: begin test50_command2 <= 16'h55; xpc10nz <= 4'd13/*xpc10nz*/; end 5'd28/*US*/: begin test50_command2 <= 16'h50; xpc10nz <= 4'd12/*xpc10nz*/; end 5'd29/*US*/: begin test50_command2 <= 16'h53; xpc10nz <= 4'd11/*xpc10nz*/; end 5'd30/*US*/: begin Ttte0_12_V_0 <= 32'd0; test50_command2 <= 16'h50; xpc10nz <= 4'd10/*xpc10nz*/; end 5'd31/*US*/: begin test50_command2 <= 16'h44; xpc10nz <= 4'd9/*xpc10nz*/; end endcase else case (xpc10nz) 4'd8/*US*/: xpc10nz <= 5'd31/*xpc10nz*/; 4'd9/*US*/: xpc10nz <= 5'd30/*xpc10nz*/; 4'd10/*US*/: xpc10nz <= 5'd29/*xpc10nz*/; 4'd11/*US*/: xpc10nz <= 5'd28/*xpc10nz*/; 4'd12/*US*/: xpc10nz <= 5'd27/*xpc10nz*/; 4'd13/*US*/: xpc10nz <= 5'd26/*xpc10nz*/; 4'd14/*US*/: xpc10nz <= 5'd25/*xpc10nz*/; 4'd15/*US*/: xpc10nz <= 5'd23/*xpc10nz*/; 5'd23/*US*/: xpc10nz <= 5'd23/*xpc10nz*/; 5'd25/*US*/: xpc10nz <= 5'd25/*xpc10nz*/; 5'd26/*US*/: xpc10nz <= 5'd26/*xpc10nz*/; 5'd27/*US*/: xpc10nz <= 5'd27/*xpc10nz*/; 5'd28/*US*/: xpc10nz <= 5'd28/*xpc10nz*/; 5'd29/*US*/: xpc10nz <= 5'd29/*xpc10nz*/; 5'd30/*US*/: xpc10nz <= 5'd30/*xpc10nz*/; 5'd31/*US*/: xpc10nz <= 5'd31/*xpc10nz*/; endcase case (xpc12nz) 0/*US*/: begin if (test50_exiting) xpc12nz <= -2'd1/*xpc12nz*/; if (!test50_exiting && (test50_command2==7'd83/*US*/)) begin tTsT4secondProcess_V_1 <= 32'd0; test50_sum <= 32'd0; xpc12nz <= 4'd8/*xpc12nz*/; end if (!test50_exiting && (test50_command2==7'd68/*US*/)) xpc12nz <= 1'd1/*xpc12nz*/; if ((test50_command2!=7'd73/*US*/) && !test50_exiting && (test50_command2!=7'd85/*US*/) && (test50_command2 !=7'd83/*US*/) && (test50_command2!=7'd80/*US*/) && (test50_command2!=7'd68/*US*/)) begin test50_command2 <= 16'h49; xpc12nz <= 2'd2/*xpc12nz*/; end if ((test50_command2==7'd73/*US*/) && !test50_exiting) xpc12nz <= 2'd2/*xpc12nz*/; if (!test50_exiting && (test50_command2==7'd80/*US*/)) xpc12nz <= 4'd14/*xpc12nz*/; if (!test50_exiting && (test50_command2==7'd85/*US*/)) begin tTsT4secondProcess_V_0 <= 32'd0; xpc12nz <= 3'd4/*xpc12nz*/; end end 2'd2/*US*/: begin if ((test50_command2!=7'd73/*US*/) && !test50_exiting && (test50_command2!=7'd85/*US*/) && (test50_command2!=7'd83 /*US*/) && (test50_command2!=7'd80/*US*/) && (test50_command2!=7'd68/*US*/)) xpc12nz <= 2'd2/*xpc12nz*/; if ((test50_command2==7'd73/*US*/) && test50_exiting) begin test50_command2 <= 16'h49; xpc12nz <= -2'd1/*xpc12nz*/; end case (test50_command2) 7'd68/*US*/: xpc12nz <= 2'd3/*xpc12nz*/; 7'd83/*US*/: begin tTsT4secondProcess_V_1 <= 32'd0; test50_sum <= 32'd0; xpc12nz <= 4'd8/*xpc12nz*/; end endcase if ((test50_command2==7'd73/*US*/) && !test50_exiting) xpc12nz <= 2'd2/*xpc12nz*/; if ((test50_command2==7'd80/*US*/)) xpc12nz <= 4'd14/*xpc12nz*/; if ((test50_command2!=7'd73/*US*/) && test50_exiting && (test50_command2!=7'd85/*US*/) && (test50_command2!= 7'd83/*US*/) && (test50_command2!=7'd80/*US*/) && (test50_command2!=7'd68/*US*/)) xpc12nz <= -2'd1/*xpc12nz*/; if ((test50_command2==7'd85/*US*/)) begin tTsT4secondProcess_V_0 <= 32'd0; xpc12nz <= 3'd4/*xpc12nz*/; end if ((test50_command2!=7'd73/*US*/) && (test50_command2!=7'd85/*US*/) && (test50_command2!=7'd83/*US*/) && (test50_command2!=7'd80/*US*/) && (test50_command2!=7'd68/*US*/)) test50_command2 <= 16'h49; end endcase if ((xpc10nz==5'd22/*US*/)) if ((Ttte0_12_V_0<2'd2)) begin Ttte0_12_V_0 <= 1'd1+Ttte0_12_V_0; test50_command2 <= 16'h50; xpc10nz <= 4'd10/*xpc10nz*/; end else begin Ttte0_12_V_0 <= 1'd1+Ttte0_12_V_0; test50_exiting <= 1'h1; xpc10nz <= -2'd1/*xpc10nz*/; end case (xpc12nz) 3'd4/*US*/: begin if (test50_exiting && (tTsT4secondProcess_V_0>=5'd29)) begin tTsT4secondProcess_V_0 <= 32'd1+tTsT4secondProcess_V_0; test50_command2 <= 16'h49; xpc12nz <= 3'd7/*xpc12nz*/; end if (!test50_exiting && (tTsT4secondProcess_V_0>=5'd29)) begin tTsT4secondProcess_V_0 <= 32'd1+tTsT4secondProcess_V_0; test50_command2 <= 16'h49; xpc12nz <= 3'd6/*xpc12nz*/; end if ((tTsT4secondProcess_V_0<5'd29)) begin tTsT4secondProcess_V_0 <= 32'd1+tTsT4secondProcess_V_0; xpc12nz <= 3'd5/*xpc12nz*/; end end 4'd15/*US*/: begin if (test50_exiting && (tTsT4secondProcess_V_2>=5'd29)) begin tTsT4secondProcess_V_2 <= 1'd1+tTsT4secondProcess_V_2; test50_command2 <= 16'h49; xpc12nz <= -2'd1/*xpc12nz*/; end if (!test50_exiting && (tTsT4secondProcess_V_2>=5'd29)) begin tTsT4secondProcess_V_2 <= 1'd1+tTsT4secondProcess_V_2; test50_command2 <= 16'h49; xpc12nz <= 2'd2/*xpc12nz*/; end if ((tTsT4secondProcess_V_2<5'd29)) xpc12nz <= 5'd16/*xpc12nz*/; end endcase case (xpc10nz) 0/*US*/: begin test50_exiting <= 1'h0; test50_sum <= 32'hbc_614e; test50_command2 <= 16'h78; xpc10nz <= 1'd1/*xpc10nz*/; end 1'd1/*US*/: begin Ttcl0_12_V_1 <= 32'd0; Ttcl0_12_V_0 <= 32'd31; xpc10nz <= 2'd2/*xpc10nz*/; end 2'd3/*US*/: if ((Ttcl0_12_V_1<5'd29)) begin Ttcl0_12_V_1 <= 32'd1+Ttcl0_12_V_1; Ttcl0_12_V_0 <= 32'd1+(32'hffffffff&Ttcl0_12_V_0); xpc10nz <= 3'd4/*xpc10nz*/; end else begin Ttcl0_12_V_1 <= 32'd1+Ttcl0_12_V_1; xpc10nz <= 3'd5/*xpc10nz*/; end 5'd17/*US*/: if ((Ttcl25_3_V_1<5'd29)) begin Ttcl25_3_V_1 <= 32'd1+Ttcl25_3_V_1; Ttcl25_3_V_0 <= 32'd1+(32'hffffffff&Ttcl25_3_V_0); xpc10nz <= 5'd18/*xpc10nz*/; end else begin Ttcl25_3_V_1 <= 32'd1+Ttcl25_3_V_1; xpc10nz <= 5'd19/*xpc10nz*/; end endcase if (test50_exiting) begin if ((xpc12nz==4'd14/*US*/)) xpc12nz <= -2'd1/*xpc12nz*/; end else if ((xpc12nz==4'd14/*US*/)) xpc12nz <= 2'd2/*xpc12nz*/; if (SINTCCSCALbx10ARA0RRh10shot0) begin SINTCCSCALbx10ARA0RRh10hold <= 32'bx; SINTCCSCALbx10ARA0RRh10hold <= A_SINT_CC_SCALbx10_ARA0_RDD0; SINTCCSCALbx10ARA0RRh10hold <= 32'bx; SINTCCSCALbx10ARA0RRh10hold <= A_SINT_CC_SCALbx10_ARA0_RDD0; SINTCCSCALbx10ARA0RRh10hold <= 32'bx; end if (test50_exiting && (tTsT4secondProcess_V_1>=5'd29)) case (xpc12nz) 4'd8/*US*/: xpc12nz <= 4'd12/*xpc12nz*/; 4'd13/*US*/: begin tTsT4secondProcess_V_1 <= 32'd1+tTsT4secondProcess_V_1; test50_sum <= test50_sum+((xpc12nz==4'd13/*US*/)? A_SINT_CC_SCALbx10_ARA0_RDD0: SINTCCSCALbx10ARA0RRh10hold ); test50_command2 <= 16'h49; end endcase if ((xpc12nz==4'd13/*US*/)) xpc12nz <= -2'd1/*xpc12nz*/; if (!test50_exiting && (tTsT4secondProcess_V_1>=5'd29)) case (xpc12nz) 4'd8/*US*/: xpc12nz <= 4'd10/*xpc12nz*/; 4'd11/*US*/: begin tTsT4secondProcess_V_1 <= 32'd1+tTsT4secondProcess_V_1; test50_sum <= test50_sum+((xpc12nz==4'd11/*US*/)? A_SINT_CC_SCALbx10_ARA0_RDD0: SINTCCSCALbx10ARA0RRh10hold ); test50_command2 <= 16'h49; end endcase case (xpc12nz) 4'd11/*US*/: xpc12nz <= 2'd2/*xpc12nz*/; 4'd14/*US*/: test50_command2 <= 16'h49; endcase if ((tTsT4secondProcess_V_1<5'd29) && (xpc12nz==4'd8/*US*/)) xpc12nz <= 4'd9/*xpc12nz*/; if (!test50_exiting && (test50_command2==7'd68/*US*/) && (xpc12nz==1'd1/*US*/)) tTsT4secondProcess_V_2 <= 32'd0; if ((xpc12nz==1'd1/*US*/)) xpc12nz <= 4'd15/*xpc12nz*/; if ((test50_command2==7'd68/*US*/) && (xpc12nz==2'd3/*US*/)) tTsT4secondProcess_V_2 <= 32'd0; case (xpc12nz) 2'd3/*US*/: xpc12nz <= 4'd15/*xpc12nz*/; 4'd9/*US*/: begin if ((tTsT4secondProcess_V_1<5'd29)) begin tTsT4secondProcess_V_1 <= 32'd1+tTsT4secondProcess_V_1; test50_sum <= test50_sum+((xpc12nz==4'd9/*US*/)? A_SINT_CC_SCALbx10_ARA0_RDD0: SINTCCSCALbx10ARA0RRh10hold ); end xpc12nz <= 4'd8/*xpc12nz*/; end 5'd16/*US*/: begin if ((tTsT4secondProcess_V_2<5'd29)) tTsT4secondProcess_V_2 <= 1'd1+tTsT4secondProcess_V_2; xpc12nz <= 4'd15/*xpc12nz*/; end endcase if ((xpc10nz==5'd21/*US*/)) xpc10nz <= 5'd22/*xpc10nz*/; SINTCCSCALbx10ARA0RRh10shot0 <= (test50_exiting? (xpc12nz==4'd12/*US*/) && (tTsT4secondProcess_V_1>=5'd29): (xpc12nz ==4'd10/*US*/) && (tTsT4secondProcess_V_1>=5'd29) || (xpc12nz==0/*US*/) && (test50_command2==7'd68/*US*/)) || (xpc12nz== 3'd4/*US*/) || (tTsT4secondProcess_V_2<5'd29) && (xpc12nz==4'd15/*US*/) || (xpc12nz==2'd2/*US*/) && (test50_command2==7'd68 /*US*/) || (xpc12nz==4'd8/*US*/) && (tTsT4secondProcess_V_1<5'd29); if ((xpc12nz==3'd5/*US*/)) xpc12nz <= 3'd4/*xpc12nz*/; if ((xpc12nz==3'd6/*US*/)) xpc12nz <= 2'd2/*xpc12nz*/; if ((xpc12nz==3'd7/*US*/)) xpc12nz <= -2'd1/*xpc12nz*/; if ((xpc12nz==4'd10/*US*/)) xpc12nz <= 4'd11/*xpc12nz*/; if ((xpc12nz==4'd12/*US*/)) xpc12nz <= 4'd13/*xpc12nz*/; SINTCCSCALbx10ARA0RRh10shot0 <= (xpc10nz==5'd19/*US*/) || (Ttcl0_12_V_1<5'd29) && (xpc10nz==2'd3/*US*/) || (xpc10nz ==1'd1/*US*/) || (xpc10nz==3'd5/*US*/) || (Ttcl25_3_V_1<5'd29) && (xpc10nz==5'd17/*US*/) || ((xpc10nz==4'd15/*US*/) || (xpc10nz==5'd23/*US*/)) && (test50_command2==7'd73/*US*/); if ((xpc10nz==2'd2/*US*/)) xpc10nz <= 2'd3/*xpc10nz*/; if ((xpc10nz==3'd4/*US*/)) xpc10nz <= 2'd3/*xpc10nz*/; if ((xpc10nz==3'd5/*US*/)) xpc10nz <= 3'd6/*xpc10nz*/; if ((xpc10nz==3'd6/*US*/)) xpc10nz <= 3'd7/*xpc10nz*/; if ((xpc10nz==3'd7/*US*/)) xpc10nz <= 4'd8/*xpc10nz*/; if ((xpc10nz==5'd16/*US*/)) xpc10nz <= 5'd17/*xpc10nz*/; if ((xpc10nz==5'd18/*US*/)) xpc10nz <= 5'd17/*xpc10nz*/; if ((xpc10nz==5'd19/*US*/)) xpc10nz <= 5'd20/*xpc10nz*/; if ((xpc10nz==5'd20/*US*/)) xpc10nz <= 5'd21/*xpc10nz*/; if ((xpc10nz==5'd24/*US*/)) xpc10nz <= 5'd17/*xpc10nz*/; end //End structure HPR test50.exe end CV_2P_SSRAM_FL1 #(6'd32, 3'd5, 5'd30, 6'd32) A_SINT_CC_SCALbx10_ARA0(clk, reset, A_SINT_CC_SCALbx10_ARA0_RDD0, A_SINT_CC_SCALbx10_ARA0_AD0 , A_SINT_CC_SCALbx10_ARA0_WEN0, A_SINT_CC_SCALbx10_ARA0_REN0, A_SINT_CC_SCALbx10_ARA0_WRD0, A_SINT_CC_SCALbx10_ARA0_RDD1, A_SINT_CC_SCALbx10_ARA0_AD1 , A_SINT_CC_SCALbx10_ARA0_WEN1, A_SINT_CC_SCALbx10_ARA0_REN1, A_SINT_CC_SCALbx10_ARA0_WRD1); // 1 vectors of width 6 // 5 vectors of width 1 // 4 vectors of width 32 // 3 vectors of width 5 // 1 vectors of width 16 // 256 bits in scalar variables // Total state bits in module = 426 bits. // 65 continuously assigned (wire/non-state) bits // cell CV_2P_SSRAM_FL1 count=1 // Total number of leaf cells = 1 endmodule // // LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable //HPR L/S (orangepath) auxiliary reports. //KiwiC compilation report //Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.14 : 29-May-2016 //30/05/2016 08:23:01 //Cmd line args: Z:\home\djg11\d320\hprls\kiwipro\kiwic\distro\lib\kiwic.exe -vnl-roundtrip=disable -report-each-step -kiwic-finish=enable -res2-pipelining=off -kiwic-cil-dump=separately test50.exe -sim 1800 -compose=disable -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test50.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=soft -give-backtrace -report-each-step //---------------------------------------------------------- //Report from KiwiC-fe.rpt::: //KiwiC: front end input processing of class or method called KiwiSystem/Kiwi // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor10 // //KiwiC start_thread (or entry point) id=cctor10 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+0 // //KiwiC: front end input processing of class or method called System/BitConverter // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor12 // //KiwiC start_thread (or entry point) id=cctor12 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+1 // //KiwiC: front end input processing of class or method called test50 // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor14 // //KiwiC start_thread (or entry point) id=cctor14 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+2 // //KiwiC: front end input processing of class or method called test50 // //root_compiler: start elaborating class 'test50' // //elaborating class 'test50' // //compiling static method as entry point: style=Root idl=test50/Main // //Performing root elaboration of method Main // //KiwiC start_thread (or entry point) id=Main10 // //Logging start thread entry point = CE_region(System/Threading/ThreadStart/400120%System/Threading/ThreadStart%400120%12, &(CTL_record(System/Threading/ThreadStart,...)), {cid=ThreadStart.Threading.System, marker=wondtoken, constant=true}): USER_THREAD1(CE_conv(CTL_object, Var(ktop16%test50%-1000%None, CT_cr(test50, <<NONE>>), ..., {constant=true})), CE_conv(CTL_object, CE_region(test50/secondProcess%test50/secondProcess%-3303%None, CT_arr(CTL_object, <unspec>), {cid=secondProcess.test50, marker=wondtoken, constant=true})), ()) // //Logging start thread entry point = CE_region(System/Threading/ThreadStart/400120%System/Threading/ThreadStart%400120%12, &(CTL_record(System/Threading/ThreadStart,...)), {cid=ThreadStart.Threading.System, marker=wondtoken, constant=true}): USER_THREAD1(CE_conv(CTL_object, Var(ktop16%test50%-1000%None, CT_cr(test50, <<NONE>>), ..., {constant=true})), CE_conv(CTL_object, CE_region(test50/secondProcess%test50/secondProcess%-3303%None, CT_arr(CTL_object, <unspec>), {cid=secondProcess.test50, marker=wondtoken, constant=true})), ()) // //KiwiC start_thread (or entry point) id=secondProcess10 // //root_compiler class done: test50 // //Report of all settings used from the recipe or command line: // // cil-uwind-budget=10000 // // kiwic-finish=enable // // kiwic-cil-dump=separately // // kiwic-kcode-dump=disable // // array-4d-name=KIWIARRAY4D // // array-3d-name=KIWIARRAY3D // // array-2d-name=KIWIARRAY2D // // kiwi-dll=Kiwi.dll // // kiwic-dll=Kiwic.dll // // kiwic-zerolength-arrays=disable // // kiwic-fpgaconsole-default=enable // // postgen-optimise=enable // // gtrace-loglevel=20 // // intcil-loglevel=20 // // firstpass-loglevel=20 // // root=$attributeroot // // srcfile=test50.exe // //END OF KIWIC REPORT FILE // //---------------------------------------------------------- //Report from restructure2::: //Offchip Load/Store (and other) Ports = Nothing to Report // //---------------------------------------------------------- //Report from restructure2::: //Restructure Technology Settings //*---------------------------+---------+---------------------------------------------------------------------------------* //| Key | Value | Description | //*---------------------------+---------+---------------------------------------------------------------------------------* //| int_flr_mul | 16000 | | //| fp_fl_dp_div | 5 | | //| fp_fl_dp_add | 4 | | //| fp_fl_dp_mul | 3 | | //| fp_fl_sp_div | 5 | | //| fp_fl_sp_add | 4 | | //| fp_fl_sp_mul | 3 | | //| res2-loadstore-port-count | 0 | | //| max_no_fp_muls | 6 | Maximum number of adders and subtractors (or combos) to instantiate per thread. | //| max_no_fp_muls | 6 | Maximum number of f/p dividers to instantiate per thread. | //| max_no_int_muls | 3 | Maximum number of int multipliers to instantiate per thread. | //| max_no_fp_divs | 2 | Maximum number of f/p dividers to instantiate per thread. | //| max_no_int_divs | 2 | Maximum number of int dividers to instantiate per thread. | //| res2-offchip-threshold | 1000000 | | //| res2-combrom-threshold | 64 | | //| res2-combram-threshold | 32 | | //| res2-regfile-threshold | 8 | | //*---------------------------+---------+---------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for xpc10 //*----------------------------+-----+-------------+------+------+-------+-----+-------------+--------* //| gb-flag/Pause | eno | hwm | root | exec | start | end | antecedants | next | //*----------------------------+-----+-------------+------+------+-------+-----+-------------+--------* //| X0:"xpc10:start0" | 900 | hwm=0.0.0 | 0 | 0 | - | - | --- | 1 | //| X1:"xpc10:1" | 901 | hwm=0.0.1 | 1 | 1 | 2 | 2 | --- | 3 | //| X2:"xpc10:2" | 903 | hwm=0.0.0 | 3 | 3 | - | - | --- | 5 | //| X2:"xpc10:2" | 902 | hwm=0.0.1 | 3 | 3 | 4 | 4 | --- | 3 | //| X4:"xpc10:4" | 904 | hwm=0.0.1 | 5 | 5 | 6 | 6 | --- | 7 | //| X8:"xpc10:8" | 905 | hwm=0.0.0 | 7 | 7 | - | - | --- | 8 | //| X16:"xpc10:16" | 907 | hwm=0.0.0 | 8 | 8 | - | - | --- | 9 | //| X16:"xpc10:16" | 906 | hwm=0.0.0 | 8 | 8 | - | - | --- | 31 | //| X32:"xpc10:32" | 909 | hwm=0.0.0 | 9 | 9 | - | - | --- | 10 | //| X32:"xpc10:32" | 908 | hwm=0.0.0 | 9 | 9 | - | - | --- | 30 | //| X64:"xpc10:64" | 911 | hwm=0.0.0 | 10 | 10 | - | - | --- | 11 | //| X64:"xpc10:64" | 910 | hwm=0.0.0 | 10 | 10 | - | - | --- | 29 | //| X128:"xpc10:128" | 913 | hwm=0.0.0 | 11 | 11 | - | - | --- | 12 | //| X128:"xpc10:128" | 912 | hwm=0.0.0 | 11 | 11 | - | - | --- | 28 | //| X256:"xpc10:256" | 915 | hwm=0.0.0 | 12 | 12 | - | - | --- | 13 | //| X256:"xpc10:256" | 914 | hwm=0.0.0 | 12 | 12 | - | - | --- | 27 | //| X512:"xpc10:512" | 917 | hwm=0.0.0 | 13 | 13 | - | - | --- | 14 | //| X512:"xpc10:512" | 916 | hwm=0.0.0 | 13 | 13 | - | - | --- | 26 | //| X1024:"xpc10:1024" | 919 | hwm=0.0.0 | 14 | 14 | - | - | --- | 15 | //| X1024:"xpc10:1024" | 918 | hwm=0.0.0 | 14 | 14 | - | - | --- | 25 | //| X2048:"xpc10:2048" | 921 | hwm=0.0.1 | 15 | 15 | 16 | 16 | --- | 17 | //| X2048:"xpc10:2048" | 920 | hwm=0.0.0 | 15 | 15 | - | - | --- | 23 | //| X4096:"xpc10:4096" | 923 | hwm=0.0.0 | 17 | 17 | - | - | --- | 19 | //| X4096:"xpc10:4096" | 922 | hwm=0.0.1 | 17 | 17 | 18 | 18 | --- | 17 | //| X8192:"xpc10:8192" | 924 | hwm=0.0.1 | 19 | 19 | 20 | 20 | --- | 21 | //| X16384:"xpc10:16384" | 925 | hwm=0.0.0 | 21 | 21 | - | - | --- | 22 | //| X32768:"xpc10:32768" | 927 | hwm=0.0.0 | 22 | 22 | - | - | --- | <NONE> | //| X32768:"xpc10:32768" | 926 | hwm=0.0.0 | 22 | 22 | - | - | --- | 10 | //| X65536:"xpc10:65536" | 929 | hwm=0.0.1 | 23 | 23 | 24 | 24 | --- | 17 | //| X65536:"xpc10:65536" | 928 | hwm=0.0.0 | 23 | 23 | - | - | --- | 23 | //| X131072:"xpc10:131072" | 931 | hwm=0.0.0 | 25 | 25 | - | - | --- | 15 | //| X131072:"xpc10:131072" | 930 | hwm=0.0.0 | 25 | 25 | - | - | --- | 25 | //| X262144:"xpc10:262144" | 933 | hwm=0.0.0 | 26 | 26 | - | - | --- | 14 | //| X262144:"xpc10:262144" | 932 | hwm=0.0.0 | 26 | 26 | - | - | --- | 26 | //| X524288:"xpc10:524288" | 935 | hwm=0.0.0 | 27 | 27 | - | - | --- | 13 | //| X524288:"xpc10:524288" | 934 | hwm=0.0.0 | 27 | 27 | - | - | --- | 27 | //| X1048576:"xpc10:1048576" | 937 | hwm=0.0.0 | 28 | 28 | - | - | --- | 12 | //| X1048576:"xpc10:1048576" | 936 | hwm=0.0.0 | 28 | 28 | - | - | --- | 28 | //| X2097152:"xpc10:2097152" | 939 | hwm=0.0.0 | 29 | 29 | - | - | --- | 11 | //| X2097152:"xpc10:2097152" | 938 | hwm=0.0.0 | 29 | 29 | - | - | --- | 29 | //| X4194304:"xpc10:4194304" | 941 | hwm=0.0.0 | 30 | 30 | - | - | --- | 10 | //| X4194304:"xpc10:4194304" | 940 | hwm=0.0.0 | 30 | 30 | - | - | --- | 30 | //| X8388608:"xpc10:8388608" | 943 | hwm=0.0.0 | 31 | 31 | - | - | --- | 9 | //| X8388608:"xpc10:8388608" | 942 | hwm=0.0.0 | 31 | 31 | - | - | --- | 31 | //*----------------------------+-----+-------------+------+------+-------+-----+-------------+--------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"xpc10:start0" 900 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X0:"xpc10:start0" //res2: Thread=xpc10 state=X0:"xpc10:start0" //*-----+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------* //| 0 | - | R0 CTRL | | //| 0 | 900 | R0 DATA | | //| 0+E | 900 | W0 DATA | test50_command2 te=te:0 scalarw(S16'120I) test50_sum te=te:0 scalarw(S32'12345678I) test50_exiting te=te:0 scalarw(U1'0I) PLI:Kiwi Demo - Test50 s... | //*-----+-----+---------+--------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1:"xpc10:1" 901 : major_start_pcl=1 edge_private_start/end=2/2 exec=1 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X1:"xpc10:1" //res2: Thread=xpc10 state=X1:"xpc10:1" //*-----+-----+---------+--------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+--------------------------------------------------------------------------------------------------------------------* //| 1 | - | R0 CTRL | | //| 1 | 901 | R0 DATA | | //| 1+E | 901 | W0 DATA | Ttcl0.12_V_0 te=te:1 scalarw(31) Ttcl0.12_V_1 te=te:1 scalarw(0) @_SINT/CC/SCALbx10_ARA0 te=te:1 write(0, S32'30I\ | //| | | | ) PLI: Test50 Remote Stat... PLI:Kiwi Demo - Test50 p... | //| 2 | 901 | W1 DATA | | //*-----+-----+---------+--------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"xpc10:2" 903 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"xpc10:2" 902 : major_start_pcl=3 edge_private_start/end=4/4 exec=3 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X2:"xpc10:2" //res2: Thread=xpc10 state=X2:"xpc10:2" //*-----+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| 3 | - | R0 CTRL | | //| 3 | 902 | R0 DATA | | //| 3+E | 902 | W0 DATA | Ttcl0.12_V_0 te=te:3 scalarw(1+(C(Ttcl0.12_V_0))) Ttcl0.12_V_1 te=te:3 scalarw(1+Ttcl0.12_V_1) @_SINT/CC/SCALbx10_ARA0 te=te:3 write(1+Ttcl0.12_V_1, C(Ttcl0.12_V_0)) | //| 4 | 902 | W1 DATA | | //| 3 | 903 | R0 DATA | | //| 3+E | 903 | W0 DATA | Ttcl0.12_V_1 te=te:3 scalarw(1+Ttcl0.12_V_1) | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"xpc10:4" 904 : major_start_pcl=5 edge_private_start/end=6/6 exec=5 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X4:"xpc10:4" //res2: Thread=xpc10 state=X4:"xpc10:4" //*-----+-----+---------+-----------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------* //| 5 | - | R0 CTRL | | //| 5 | 904 | R0 DATA | | //| 5+E | 904 | W0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:5 write(29, 99) | //| 6 | 904 | W1 DATA | | //*-----+-----+---------+-----------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"xpc10:8" 905 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=7 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X8:"xpc10:8" //res2: Thread=xpc10 state=X8:"xpc10:8" //*-----+-----+---------+------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------* //| 7 | - | R0 CTRL | | //| 7 | 905 | R0 DATA | | //| 7+E | 905 | W0 DATA | | //*-----+-----+---------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"xpc10:16" 907 : major_start_pcl=8 edge_private_start/end=-1/-1 exec=8 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"xpc10:16" 906 : major_start_pcl=8 edge_private_start/end=-1/-1 exec=8 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X16:"xpc10:16" //res2: Thread=xpc10 state=X16:"xpc10:16" //*-----+-----+---------+------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------------------------------------------* //| 8 | - | R0 CTRL | | //| 8 | 906 | R0 DATA | | //| 8+E | 906 | W0 DATA | | //| 8 | 907 | R0 DATA | | //| 8+E | 907 | W0 DATA | test50_command2 te=te:8 scalarw(S16'68I) | //*-----+-----+---------+------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"xpc10:32" 909 : major_start_pcl=9 edge_private_start/end=-1/-1 exec=9 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"xpc10:32" 908 : major_start_pcl=9 edge_private_start/end=-1/-1 exec=9 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32:"xpc10:32" //res2: Thread=xpc10 state=X32:"xpc10:32" //*-----+-----+---------+-------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-------------------------------------------------------------------------------------------------------* //| 9 | - | R0 CTRL | | //| 9 | 908 | R0 DATA | | //| 9+E | 908 | W0 DATA | | //| 9 | 909 | R0 DATA | | //| 9+E | 909 | W0 DATA | test50_command2 te=te:9 scalarw(S16'80I) Ttte0.12_V_0 te=te:9 scalarw(0) PLI: Test50 fancy=%u rs... | //*-----+-----+---------+-------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"xpc10:64" 911 : major_start_pcl=10 edge_private_start/end=-1/-1 exec=10 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X64:"xpc10:64" 910 : major_start_pcl=10 edge_private_start/end=-1/-1 exec=10 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X64:"xpc10:64" //res2: Thread=xpc10 state=X64:"xpc10:64" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 10 | - | R0 CTRL | | //| 10 | 910 | R0 DATA | | //| 10+E | 910 | W0 DATA | | //| 10 | 911 | R0 DATA | | //| 10+E | 911 | W0 DATA | test50_command2 te=te:10 scalarw(S16'83I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X128:"xpc10:128" 913 : major_start_pcl=11 edge_private_start/end=-1/-1 exec=11 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X128:"xpc10:128" 912 : major_start_pcl=11 edge_private_start/end=-1/-1 exec=11 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X128:"xpc10:128" //res2: Thread=xpc10 state=X128:"xpc10:128" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 11 | - | R0 CTRL | | //| 11 | 912 | R0 DATA | | //| 11+E | 912 | W0 DATA | | //| 11 | 913 | R0 DATA | | //| 11+E | 913 | W0 DATA | test50_command2 te=te:11 scalarw(S16'80I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X256:"xpc10:256" 915 : major_start_pcl=12 edge_private_start/end=-1/-1 exec=12 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X256:"xpc10:256" 914 : major_start_pcl=12 edge_private_start/end=-1/-1 exec=12 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X256:"xpc10:256" //res2: Thread=xpc10 state=X256:"xpc10:256" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 12 | - | R0 CTRL | | //| 12 | 914 | R0 DATA | | //| 12+E | 914 | W0 DATA | | //| 12 | 915 | R0 DATA | | //| 12+E | 915 | W0 DATA | test50_command2 te=te:12 scalarw(S16'85I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X512:"xpc10:512" 917 : major_start_pcl=13 edge_private_start/end=-1/-1 exec=13 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X512:"xpc10:512" 916 : major_start_pcl=13 edge_private_start/end=-1/-1 exec=13 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X512:"xpc10:512" //res2: Thread=xpc10 state=X512:"xpc10:512" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 13 | - | R0 CTRL | | //| 13 | 916 | R0 DATA | | //| 13+E | 916 | W0 DATA | | //| 13 | 917 | R0 DATA | | //| 13+E | 917 | W0 DATA | test50_command2 te=te:13 scalarw(S16'83I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1024:"xpc10:1024" 919 : major_start_pcl=14 edge_private_start/end=-1/-1 exec=14 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1024:"xpc10:1024" 918 : major_start_pcl=14 edge_private_start/end=-1/-1 exec=14 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1024:"xpc10:1024" //res2: Thread=xpc10 state=X1024:"xpc10:1024" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 14 | - | R0 CTRL | | //| 14 | 918 | R0 DATA | | //| 14+E | 918 | W0 DATA | | //| 14 | 919 | R0 DATA | | //| 14+E | 919 | W0 DATA | test50_command2 te=te:14 scalarw(S16'80I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2048:"xpc10:2048" 921 : major_start_pcl=15 edge_private_start/end=16/16 exec=15 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2048:"xpc10:2048" 920 : major_start_pcl=15 edge_private_start/end=-1/-1 exec=15 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X2048:"xpc10:2048" //res2: Thread=xpc10 state=X2048:"xpc10:2048" //*------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------* //| 15 | - | R0 CTRL | | //| 15 | 920 | R0 DATA | | //| 15+E | 920 | W0 DATA | | //| 15 | 921 | R0 DATA | | //| 15+E | 921 | W0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:15 write(0, C(40+Ttte0.12_V_0)) Ttcl25.3_V_0 te=te:15 scalarw(1+(C(40+Ttte0.12_V_0))) Ttcl25.3_V_1 te=te:15 scalarw(0) | //| 16 | 921 | W1 DATA | | //*------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4096:"xpc10:4096" 923 : major_start_pcl=17 edge_private_start/end=-1/-1 exec=17 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4096:"xpc10:4096" 922 : major_start_pcl=17 edge_private_start/end=18/18 exec=17 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X4096:"xpc10:4096" //res2: Thread=xpc10 state=X4096:"xpc10:4096" //*------+-----+---------+------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------------------------------------------------------------------------* //| 17 | - | R0 CTRL | | //| 17 | 922 | R0 DATA | | //| 17+E | 922 | W0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:17 write(1+Ttcl25.3_V_1, C(Ttcl25.3_V_0)) Ttcl25.3_V_0 te=te:17 scalarw(1+(C(Ttcl\ | //| | | | 25.3_V_0))) Ttcl25.3_V_1 te=te:17 scalarw(1+Ttcl25.3_V_1) | //| 18 | 922 | W1 DATA | | //| 17 | 923 | R0 DATA | | //| 17+E | 923 | W0 DATA | Ttcl25.3_V_1 te=te:17 scalarw(1+Ttcl25.3_V_1) | //*------+-----+---------+------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8192:"xpc10:8192" 924 : major_start_pcl=19 edge_private_start/end=20/20 exec=19 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X8192:"xpc10:8192" //res2: Thread=xpc10 state=X8192:"xpc10:8192" //*------+-----+---------+------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------* //| 19 | - | R0 CTRL | | //| 19 | 924 | R0 DATA | | //| 19+E | 924 | W0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:19 write(29, 99) | //| 20 | 924 | W1 DATA | | //*------+-----+---------+------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16384:"xpc10:16384" 925 : major_start_pcl=21 edge_private_start/end=-1/-1 exec=21 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X16384:"xpc10:16384" //res2: Thread=xpc10 state=X16384:"xpc10:16384" //*------+-----+---------+-----------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------* //| 21 | - | R0 CTRL | | //| 21 | 925 | R0 DATA | | //| 21+E | 925 | W0 DATA | PLI: point2 %c %u. | //*------+-----+---------+-----------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32768:"xpc10:32768" 927 : major_start_pcl=22 edge_private_start/end=-1/-1 exec=22 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32768:"xpc10:32768" 926 : major_start_pcl=22 edge_private_start/end=-1/-1 exec=22 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32768:"xpc10:32768" //res2: Thread=xpc10 state=X32768:"xpc10:32768" //*------+-----+---------+---------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------------------------------------------------------------------------------------------------* //| 22 | - | R0 CTRL | | //| 22 | 926 | R0 DATA | | //| 22+E | 926 | W0 DATA | test50_command2 te=te:22 scalarw(S16'80I) Ttte0.12_V_0 te=te:22 scalarw(1+Ttte0.12_V_0) PLI: Test50 fancy=%u rs... | //| 22 | 927 | R0 DATA | | //| 22+E | 927 | W0 DATA | test50_exiting te=te:22 scalarw(U1'1I) Ttte0.12_V_0 te=te:22 scalarw(1+Ttte0.12_V_0) PLI:GSAI:hpr_sysexit PLI:Test50 d\ | //| | | | one. PLI:Test50 starting join... PLI:Finished main proces... | //*------+-----+---------+---------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X65536:"xpc10:65536" 929 : major_start_pcl=23 edge_private_start/end=24/24 exec=23 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X65536:"xpc10:65536" 928 : major_start_pcl=23 edge_private_start/end=-1/-1 exec=23 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X65536:"xpc10:65536" //res2: Thread=xpc10 state=X65536:"xpc10:65536" //*------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------* //| 23 | - | R0 CTRL | | //| 23 | 928 | R0 DATA | | //| 23+E | 928 | W0 DATA | | //| 23 | 929 | R0 DATA | | //| 23+E | 929 | W0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:23 write(0, C(40+Ttte0.12_V_0)) Ttcl25.3_V_0 te=te:23 scalarw(1+(C(40+Ttte0.12_V_0))) Ttcl25.3_V_1 te=te:23 scalarw(0) | //| 24 | 929 | W1 DATA | | //*------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X131072:"xpc10:131072" 931 : major_start_pcl=25 edge_private_start/end=-1/-1 exec=25 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X131072:"xpc10:131072" 930 : major_start_pcl=25 edge_private_start/end=-1/-1 exec=25 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X131072:"xpc10:131072" //res2: Thread=xpc10 state=X131072:"xpc10:131072" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 25 | - | R0 CTRL | | //| 25 | 930 | R0 DATA | | //| 25+E | 930 | W0 DATA | | //| 25 | 931 | R0 DATA | | //| 25+E | 931 | W0 DATA | test50_command2 te=te:25 scalarw(S16'80I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X262144:"xpc10:262144" 933 : major_start_pcl=26 edge_private_start/end=-1/-1 exec=26 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X262144:"xpc10:262144" 932 : major_start_pcl=26 edge_private_start/end=-1/-1 exec=26 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X262144:"xpc10:262144" //res2: Thread=xpc10 state=X262144:"xpc10:262144" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 26 | - | R0 CTRL | | //| 26 | 932 | R0 DATA | | //| 26+E | 932 | W0 DATA | | //| 26 | 933 | R0 DATA | | //| 26+E | 933 | W0 DATA | test50_command2 te=te:26 scalarw(S16'83I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"xpc10:524288" 935 : major_start_pcl=27 edge_private_start/end=-1/-1 exec=27 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X524288:"xpc10:524288" 934 : major_start_pcl=27 edge_private_start/end=-1/-1 exec=27 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X524288:"xpc10:524288" //res2: Thread=xpc10 state=X524288:"xpc10:524288" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 27 | - | R0 CTRL | | //| 27 | 934 | R0 DATA | | //| 27+E | 934 | W0 DATA | | //| 27 | 935 | R0 DATA | | //| 27+E | 935 | W0 DATA | test50_command2 te=te:27 scalarw(S16'85I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1048576:"xpc10:1048576" 937 : major_start_pcl=28 edge_private_start/end=-1/-1 exec=28 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1048576:"xpc10:1048576" 936 : major_start_pcl=28 edge_private_start/end=-1/-1 exec=28 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1048576:"xpc10:1048576" //res2: Thread=xpc10 state=X1048576:"xpc10:1048576" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 28 | - | R0 CTRL | | //| 28 | 936 | R0 DATA | | //| 28+E | 936 | W0 DATA | | //| 28 | 937 | R0 DATA | | //| 28+E | 937 | W0 DATA | test50_command2 te=te:28 scalarw(S16'80I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2097152:"xpc10:2097152" 939 : major_start_pcl=29 edge_private_start/end=-1/-1 exec=29 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2097152:"xpc10:2097152" 938 : major_start_pcl=29 edge_private_start/end=-1/-1 exec=29 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X2097152:"xpc10:2097152" //res2: Thread=xpc10 state=X2097152:"xpc10:2097152" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 29 | - | R0 CTRL | | //| 29 | 938 | R0 DATA | | //| 29+E | 938 | W0 DATA | | //| 29 | 939 | R0 DATA | | //| 29+E | 939 | W0 DATA | test50_command2 te=te:29 scalarw(S16'83I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4194304:"xpc10:4194304" 941 : major_start_pcl=30 edge_private_start/end=-1/-1 exec=30 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4194304:"xpc10:4194304" 940 : major_start_pcl=30 edge_private_start/end=-1/-1 exec=30 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X4194304:"xpc10:4194304" //res2: Thread=xpc10 state=X4194304:"xpc10:4194304" //*------+-----+---------+---------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------------------------------------------------------------------------------* //| 30 | - | R0 CTRL | | //| 30 | 940 | R0 DATA | | //| 30+E | 940 | W0 DATA | | //| 30 | 941 | R0 DATA | | //| 30+E | 941 | W0 DATA | test50_command2 te=te:30 scalarw(S16'80I) Ttte0.12_V_0 te=te:30 scalarw(0) PLI: Test50 fancy=%u rs... | //*------+-----+---------+---------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8388608:"xpc10:8388608" 943 : major_start_pcl=31 edge_private_start/end=-1/-1 exec=31 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8388608:"xpc10:8388608" 942 : major_start_pcl=31 edge_private_start/end=-1/-1 exec=31 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X8388608:"xpc10:8388608" //res2: Thread=xpc10 state=X8388608:"xpc10:8388608" //*------+-----+---------+-------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------* //| 31 | - | R0 CTRL | | //| 31 | 942 | R0 DATA | | //| 31+E | 942 | W0 DATA | | //| 31 | 943 | R0 DATA | | //| 31+E | 943 | W0 DATA | test50_command2 te=te:31 scalarw(S16'68I) | //*------+-----+---------+-------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for xpc12 //*---------------------+-----+-------------+------+------+-------+-----+-------------+--------* //| gb-flag/Pause | eno | hwm | root | exec | start | end | antecedants | next | //*---------------------+-----+-------------+------+------+-------+-----+-------------+--------* //| X0:"xpc12:start0" | 950 | hwm=0.0.0 | 0 | 0 | - | - | --- | <NONE> | //| X0:"xpc12:start0" | 949 | hwm=0.0.0 | 0 | 0 | - | - | --- | 2 | //| X0:"xpc12:start0" | 948 | hwm=0.0.0 | 0 | 0 | - | - | --- | 4 | //| X0:"xpc12:start0" | 947 | hwm=0.0.0 | 0 | 0 | - | - | --- | 8 | //| X0:"xpc12:start0" | 946 | hwm=0.0.0 | 0 | 0 | - | - | --- | 14 | //| X0:"xpc12:start0" | 945 | hwm=0.1.0 | 0 | 1 | 1 | 1 | --- | 15 | //| X0:"xpc12:start0" | 944 | hwm=0.0.0 | 0 | 0 | - | - | --- | 2 | //| X1:"xpc12:1" | 958 | hwm=0.0.0 | 2 | 2 | - | - | --- | <NONE> | //| X1:"xpc12:1" | 957 | hwm=0.0.0 | 2 | 2 | - | - | --- | 2 | //| X1:"xpc12:1" | 956 | hwm=0.0.0 | 2 | 2 | - | - | --- | 4 | //| X1:"xpc12:1" | 955 | hwm=0.0.0 | 2 | 2 | - | - | --- | 8 | //| X1:"xpc12:1" | 954 | hwm=0.0.0 | 2 | 2 | - | - | --- | 14 | //| X1:"xpc12:1" | 953 | hwm=0.1.0 | 2 | 3 | 3 | 3 | --- | 15 | //| X1:"xpc12:1" | 952 | hwm=0.0.0 | 2 | 2 | - | - | --- | <NONE> | //| X1:"xpc12:1" | 951 | hwm=0.0.0 | 2 | 2 | - | - | --- | 2 | //| X2:"xpc12:2" | 961 | hwm=0.0.1 | 4 | 4 | 7 | 7 | --- | <NONE> | //| X2:"xpc12:2" | 960 | hwm=0.0.1 | 4 | 4 | 6 | 6 | --- | 2 | //| X2:"xpc12:2" | 959 | hwm=0.0.1 | 4 | 4 | 5 | 5 | --- | 4 | //| X4:"xpc12:4" | 964 | hwm=0.2.0 | 8 | 13 | 12 | 13 | --- | <NONE> | //| X4:"xpc12:4" | 963 | hwm=0.2.0 | 8 | 11 | 10 | 11 | --- | 2 | //| X4:"xpc12:4" | 962 | hwm=0.1.0 | 8 | 9 | 9 | 9 | --- | 8 | //| X8:"xpc12:8" | 966 | hwm=0.0.0 | 14 | 14 | - | - | --- | <NONE> | //| X8:"xpc12:8" | 965 | hwm=0.0.0 | 14 | 14 | - | - | --- | 2 | //| X16:"xpc12:16" | 969 | hwm=0.0.0 | 15 | 15 | - | - | --- | <NONE> | //| X16:"xpc12:16" | 968 | hwm=0.0.0 | 15 | 15 | - | - | --- | 2 | //| X16:"xpc12:16" | 967 | hwm=0.1.0 | 15 | 16 | 16 | 16 | --- | 15 | //*---------------------+-----+-------------+------+------+-------+-----+-------------+--------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 950 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 949 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 948 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 947 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 946 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 945 : major_start_pcl=0 edge_private_start/end=1/1 exec=1 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X0:"xpc12:start0" 944 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: Thread=xpc12 state=X0:"xpc12:start0" //res2: Thread=xpc12 state=X0:"xpc12:start0" //*-----+-----+---------+-------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-------------------------------------------------------------------------* //| 0 | - | R0 CTRL | | //| 0 | 944 | R0 DATA | | //| 0+E | 944 | W0 DATA | test50_command2 te=te:0 scalarw(S16'73I) | //| 0 | 945 | R0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:0 read(0) | //| 1 | 945 | R1 DATA | | //| 1+E | 945 | W0 DATA | tTsT4secondProcess_V_2 te=te:1 scalarw(0) PLI:sp: Print data: shar... | //| 0 | 946 | R0 DATA | | //| 0+E | 946 | W0 DATA | PLI:sp: data sum %u | //| 0 | 947 | R0 DATA | | //| 0+E | 947 | W0 DATA | test50_sum te=te:0 scalarw(0) tTsT4secondProcess_V_1 te=te:0 scalarw(0) | //| 0 | 948 | R0 DATA | | //| 0+E | 948 | W0 DATA | tTsT4secondProcess_V_0 te=te:0 scalarw(0) | //| 0 | 949 | R0 DATA | | //| 0+E | 949 | W0 DATA | | //| 0 | 950 | R0 DATA | | //| 0+E | 950 | W0 DATA | PLI:GSAI:hpr_sysexit | //*-----+-----+---------+-------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 958 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 957 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 956 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 955 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 954 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 953 : major_start_pcl=2 edge_private_start/end=3/3 exec=3 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 952 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X1:"xpc12:1" 951 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //Simple greedy schedule for res2: Thread=xpc12 state=X1:"xpc12:1" //res2: Thread=xpc12 state=X1:"xpc12:1" //*-----+-----+---------+-------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-------------------------------------------------------------------------* //| 2 | - | R0 CTRL | | //| 2 | 951 | R0 DATA | | //| 2+E | 951 | W0 DATA | test50_command2 te=te:2 scalarw(S16'73I) | //| 2 | 952 | R0 DATA | | //| 2+E | 952 | W0 DATA | test50_command2 te=te:2 scalarw(S16'73I) PLI:GSAI:hpr_sysexit | //| 2 | 953 | R0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:2 read(0) | //| 3 | 953 | R1 DATA | | //| 3+E | 953 | W0 DATA | tTsT4secondProcess_V_2 te=te:3 scalarw(0) PLI:sp: Print data: shar... | //| 2 | 954 | R0 DATA | | //| 2+E | 954 | W0 DATA | PLI:sp: data sum %u | //| 2 | 955 | R0 DATA | | //| 2+E | 955 | W0 DATA | test50_sum te=te:2 scalarw(0) tTsT4secondProcess_V_1 te=te:2 scalarw(0) | //| 2 | 956 | R0 DATA | | //| 2+E | 956 | W0 DATA | tTsT4secondProcess_V_0 te=te:2 scalarw(0) | //| 2 | 957 | R0 DATA | | //| 2+E | 957 | W0 DATA | | //| 2 | 958 | R0 DATA | | //| 2+E | 958 | W0 DATA | test50_command2 te=te:2 scalarw(S16'73I) PLI:GSAI:hpr_sysexit | //*-----+-----+---------+-------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X2:"xpc12:2" 961 : major_start_pcl=4 edge_private_start/end=7/7 exec=4 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X2:"xpc12:2" 960 : major_start_pcl=4 edge_private_start/end=6/6 exec=4 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X2:"xpc12:2" 959 : major_start_pcl=4 edge_private_start/end=5/5 exec=4 (dend=1) //Simple greedy schedule for res2: Thread=xpc12 state=X2:"xpc12:2" //res2: Thread=xpc12 state=X2:"xpc12:2" //*-----+-----+---------+----------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+----------------------------------------------------------------------------------------------------------------------------------* //| 4 | - | R0 CTRL | | //| 4 | 959 | R0 DATA | | //| 4+E | 959 | W0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:4 write(tTsT4secondProcess_V_0, E1) tTsT4secondProcess_V_0 te=te:4 scalarw(1+tTsT4secondProcess_V\ | //| | | | _0) | //| 5 | 959 | W1 DATA | | //| 4 | 960 | R0 DATA | | //| 4+E | 960 | W0 DATA | test50_command2 te=te:4 scalarw(S16'73I) @_SINT/CC/SCALbx10_ARA0 te=te:4 write(tTsT4secondProcess_V_0, E1) tTsT4secondProcess_V\ | //| | | | _0 te=te:4 scalarw(1+tTsT4secondProcess_V_0) | //| 6 | 960 | W1 DATA | | //| 4 | 961 | R0 DATA | | //| 4+E | 961 | W0 DATA | test50_command2 te=te:4 scalarw(S16'73I) @_SINT/CC/SCALbx10_ARA0 te=te:4 write(tTsT4secondProcess_V_0, E1) tTsT4secondProcess_V\ | //| | | | _0 te=te:4 scalarw(1+tTsT4secondProcess_V_0) PLI:GSAI:hpr_sysexit | //| 7 | 961 | W1 DATA | | //*-----+-----+---------+----------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X4:"xpc12:4" 964 : major_start_pcl=8 edge_private_start/end=12/13 exec=13 (dend=2) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X4:"xpc12:4" 963 : major_start_pcl=8 edge_private_start/end=10/11 exec=11 (dend=2) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X4:"xpc12:4" 962 : major_start_pcl=8 edge_private_start/end=9/9 exec=9 (dend=1) //Simple greedy schedule for res2: Thread=xpc12 state=X4:"xpc12:4" //res2: Thread=xpc12 state=X4:"xpc12:4" //*------+-----+---------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------* //| 8 | - | R0 CTRL | | //| 8 | 962 | R0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:8 read(tTsT4secondProcess_V_1) | //| 9 | 962 | R1 DATA | | //| 9+E | 962 | W0 DATA | test50_sum te=te:9 scalarw(E2) tTsT4secondProcess_V_1 te=te:9 scalarw(1+tTsT4secondProcess_V_1) | //| 8 | 963 | R0 DATA | | //| 10 | 963 | R1 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:10 read(tTsT4secondProcess_V_1) | //| 11 | 963 | R2 DATA | | //| 11+E | 963 | W0 DATA | test50_command2 te=te:11 scalarw(S16'73I) test50_sum te=te:11 scalarw(E2) tTsT4secondProcess_V_1 te=te:11 scalarw(1+tTsT4secondProcess_V_1) | //| 8 | 964 | R0 DATA | | //| 12 | 964 | R1 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:12 read(tTsT4secondProcess_V_1) | //| 13 | 964 | R2 DATA | | //| 13+E | 964 | W0 DATA | test50_command2 te=te:13 scalarw(S16'73I) test50_sum te=te:13 scalarw(E2) tTsT4secondProcess_V_1 te=te:13 scalarw(1+tTsT4secondProcess_V_1) PLI:GSAI:hpr_sysexit | //*------+-----+---------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X8:"xpc12:8" 966 : major_start_pcl=14 edge_private_start/end=-1/-1 exec=14 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X8:"xpc12:8" 965 : major_start_pcl=14 edge_private_start/end=-1/-1 exec=14 (dend=0) //Simple greedy schedule for res2: Thread=xpc12 state=X8:"xpc12:8" //res2: Thread=xpc12 state=X8:"xpc12:8" //*------+-----+---------+-----------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------------------------------------* //| 14 | - | R0 CTRL | | //| 14 | 965 | R0 DATA | | //| 14+E | 965 | W0 DATA | test50_command2 te=te:14 scalarw(S16'73I) | //| 14 | 966 | R0 DATA | | //| 14+E | 966 | W0 DATA | test50_command2 te=te:14 scalarw(S16'73I) PLI:GSAI:hpr_sysexit | //*------+-----+---------+-----------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X16:"xpc12:16" 969 : major_start_pcl=15 edge_private_start/end=-1/-1 exec=15 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X16:"xpc12:16" 968 : major_start_pcl=15 edge_private_start/end=-1/-1 exec=15 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc12 state=X16:"xpc12:16" 967 : major_start_pcl=15 edge_private_start/end=16/16 exec=16 (dend=1) //Simple greedy schedule for res2: Thread=xpc12 state=X16:"xpc12:16" //res2: Thread=xpc12 state=X16:"xpc12:16" //*------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------* //| 15 | - | R0 CTRL | | //| 15 | 967 | R0 DATA | @_SINT/CC/SCALbx10_ARA0 te=te:15 read(1+tTsT4secondProcess_V_2) | //| 16 | 967 | R1 DATA | | //| 16+E | 967 | W0 DATA | tTsT4secondProcess_V_2 te=te:16 scalarw(1+tTsT4secondProcess_V_2) PLI:sp: Print data: shar... | //| 15 | 968 | R0 DATA | | //| 15+E | 968 | W0 DATA | test50_command2 te=te:15 scalarw(S16'73I) tTsT4secondProcess_V_2 te=te:15 scalarw(1+tTsT4secondProcess_V_2) | //| 15 | 969 | R0 DATA | | //| 15+E | 969 | W0 DATA | test50_command2 te=te:15 scalarw(S16'73I) tTsT4secondProcess_V_2 te=te:15 scalarw(1+tTsT4secondProcess_V_2) PLI:GSAI:hpr_sysexit | //*------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from verilog_render::: //1 vectors of width 6 // //5 vectors of width 1 // //4 vectors of width 32 // //3 vectors of width 5 // //1 vectors of width 16 // //256 bits in scalar variables // //Total state bits in module = 426 bits. // //65 continuously assigned (wire/non-state) bits // //Total number of leaf cells = 0 // // eof (HPR L/S Verilog)