// CBG Orangepath HPR L/S System // Verilog output file generated at 29/11/2016 10:06:49 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 0.2.16p : 24th-November-2016 Unix 3.13.0.65 // /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -kiwic-register-colours=1 -give-backtrace -vnl-resets=synchronous -vnl-roundtrip=disable -kiwic-cil-dump=combined -kiwic-kcode-dump=enable -bevelab-default-pause-mode=bblock -res2-loadstore-port-count=0 -repack-to-roms=enable Primes.exe Kiwi_vb.dll -root=Primes.Main -vnl=Primes.v `timescale 1ns/1ns module Primes(input clk, input reset); integer T404_Primes_Printer_0_12_V_0_GP; integer T404_Primes_Printer_0_12_V_1_GP; reg [3:0] xpc10nz; reg [13:0] A_BOOL_CC_SCALbx10_ARA0_AD0; reg A_BOOL_CC_SCALbx10_ARA0_WRD0; reg A_BOOL_CC_SCALbx10_ARA0_WEN0; wire A_BOOL_CC_SCALbx10_ARA0_RDD0; reg A_BOOL_CC_SCALbx10_ARA0_REN0; reg BOOLCCSCALbx10ARA0RRh10hold; reg BOOLCCSCALbx10ARA0RRh10shot0; always @(* ) begin A_BOOL_CC_SCALbx10_ARA0_AD0 = 32'sd0; A_BOOL_CC_SCALbx10_ARA0_WRD0 = 32'sd0; A_BOOL_CC_SCALbx10_ARA0_REN0 = 32'sd0; A_BOOL_CC_SCALbx10_ARA0_WEN0 = 32'sd0; A_BOOL_CC_SCALbx10_ARA0_WEN0 = (T404_Primes_Printer_0_12_V_0_GP<32'sh_2710) && (xpc10nz==4'sd2/*2:xpc10nz*/) || (T404_Primes_Printer_0_12_V_1_GP <32'sh_2710) && (xpc10nz==4'sd5/*5:xpc10nz*/); A_BOOL_CC_SCALbx10_ARA0_REN0 = ((xpc10nz==4'sd7/*7:xpc10nz*/)? 32'd1: 32'd0); if ((T404_Primes_Printer_0_12_V_0_GP<32'sh_2710) && (xpc10nz==4'sd2/*2:xpc10nz*/)) begin A_BOOL_CC_SCALbx10_ARA0_WRD0 = 1'h1; A_BOOL_CC_SCALbx10_ARA0_AD0 = T404_Primes_Printer_0_12_V_0_GP; end if ((T404_Primes_Printer_0_12_V_1_GP<32'sh_2710) && (xpc10nz==4'sd5/*5:xpc10nz*/)) begin A_BOOL_CC_SCALbx10_ARA0_WRD0 = 1'h0; A_BOOL_CC_SCALbx10_ARA0_AD0 = T404_Primes_Printer_0_12_V_1_GP; end if ((xpc10nz==4'sd7/*7:xpc10nz*/)) A_BOOL_CC_SCALbx10_ARA0_AD0 = T404_Primes_Printer_0_12_V_1_GP; end always @(posedge clk ) begin //Start structure HPR Primes if (reset) begin T404_Primes_Printer_0_12_V_1_GP <= 32'd0; T404_Primes_Printer_0_12_V_0_GP <= 32'd0; BOOLCCSCALbx10ARA0RRh10hold <= 32'd0; BOOLCCSCALbx10ARA0RRh10shot0 <= 32'd0; xpc10nz <= 32'd0; end else begin if ((xpc10nz==4'sd8/*8:xpc10nz*/)) begin if ((T404_Primes_Printer_0_12_V_1_GP>=32'sh_2710)) begin $display("There are %1d primes below %1d.", T404_Primes_Printer_0_12_V_0_GP, 32'sh_2710); $display("Primes End:"); $finish(32'sd0); end if (((xpc10nz==4'sd8/*8:xpc10nz*/)? A_BOOL_CC_SCALbx10_ARA0_RDD0: BOOLCCSCALbx10ARA0RRh10hold) && (T404_Primes_Printer_0_12_V_1_GP <32'sh_2710)) $display(" %1d is prime", T404_Primes_Printer_0_12_V_1_GP); end if ((T404_Primes_Printer_0_12_V_0_GP>=32'sh_2710)) case (xpc10nz) 4'sd2/*2:xpc10nz*/: $display("Crossings Off Flags"); 4'sd4/*4:xpc10nz*/: $display("Printing out the primes:"); endcase case (xpc10nz) 4'sd0/*0:xpc10nz*/: $display("Primes Start:"); 4'sd1/*1:xpc10nz*/: $display("Setting All Flags"); endcase if ((T404_Primes_Printer_0_12_V_0_GP<32'sh_2710)) case (xpc10nz) 4'sd2/*2:xpc10nz*/: begin T404_Primes_Printer_0_12_V_0_GP <= 32'sd1+T404_Primes_Printer_0_12_V_0_GP; xpc10nz <= 4'sd3/*3:xpc10nz*/; end 4'sd4/*4:xpc10nz*/: begin T404_Primes_Printer_0_12_V_1_GP <= 32'sd2*T404_Primes_Printer_0_12_V_0_GP; xpc10nz <= 4'sd5/*5:xpc10nz*/; end endcase else case (xpc10nz) 4'sd2/*2:xpc10nz*/: begin T404_Primes_Printer_0_12_V_0_GP <= 32'sd2; xpc10nz <= 4'sd4/*4:xpc10nz*/; end 4'sd4/*4:xpc10nz*/: begin T404_Primes_Printer_0_12_V_1_GP <= 32'sd0; T404_Primes_Printer_0_12_V_0_GP <= 32'sd0; xpc10nz <= 4'sd7/*7:xpc10nz*/; end endcase if ((xpc10nz==4'sd8/*8:xpc10nz*/)) begin if ((T404_Primes_Printer_0_12_V_1_GP>=32'sh_2710)) xpc10nz <= 4'sd7/*7:xpc10nz*/; if (((xpc10nz==4'sd8/*8:xpc10nz*/)? A_BOOL_CC_SCALbx10_ARA0_RDD0: BOOLCCSCALbx10ARA0RRh10hold) && (T404_Primes_Printer_0_12_V_1_GP <32'sh_2710)) begin T404_Primes_Printer_0_12_V_0_GP <= 32'sd1+T404_Primes_Printer_0_12_V_0_GP; xpc10nz <= 4'sd9/*9:xpc10nz*/; end if (((xpc10nz==4'sd8/*8:xpc10nz*/)? !A_BOOL_CC_SCALbx10_ARA0_RDD0: !BOOLCCSCALbx10ARA0RRh10hold) && (T404_Primes_Printer_0_12_V_1_GP <32'sh_2710)) xpc10nz <= 4'sd9/*9:xpc10nz*/; end if ((T404_Primes_Printer_0_12_V_1_GP<32'sh_2710)) begin if ((xpc10nz==4'sd5/*5:xpc10nz*/)) begin T404_Primes_Printer_0_12_V_1_GP <= T404_Primes_Printer_0_12_V_0_GP+T404_Primes_Printer_0_12_V_1_GP; xpc10nz <= 4'sd6/*6:xpc10nz*/; end end else if ((xpc10nz==4'sd5/*5:xpc10nz*/)) begin T404_Primes_Printer_0_12_V_0_GP <= 32'sd1+T404_Primes_Printer_0_12_V_0_GP; xpc10nz <= 4'sd4/*4:xpc10nz*/; end case (xpc10nz) 4'sd0/*0:xpc10nz*/: xpc10nz <= 4'sd1/*1:xpc10nz*/; 4'sd1/*1:xpc10nz*/: begin T404_Primes_Printer_0_12_V_0_GP <= 32'sd0; xpc10nz <= 4'sd2/*2:xpc10nz*/; end 4'sd9/*9:xpc10nz*/: begin T404_Primes_Printer_0_12_V_1_GP <= 32'sd1+T404_Primes_Printer_0_12_V_1_GP; xpc10nz <= 4'sd7/*7:xpc10nz*/; end endcase if (BOOLCCSCALbx10ARA0RRh10shot0) BOOLCCSCALbx10ARA0RRh10hold <= A_BOOL_CC_SCALbx10_ARA0_RDD0; case (xpc10nz) 4'sd3/*3:xpc10nz*/: xpc10nz <= 4'sd2/*2:xpc10nz*/; 4'sd6/*6:xpc10nz*/: xpc10nz <= 4'sd5/*5:xpc10nz*/; 4'sd7/*7:xpc10nz*/: xpc10nz <= 4'sd8/*8:xpc10nz*/; endcase BOOLCCSCALbx10ARA0RRh10shot0 <= (xpc10nz==4'sd7/*7:xpc10nz*/); end //End structure HPR Primes end CV_SP_SSRAM_FL1 #(32'sd1, 32'sd14, 32'sd10000, 32'sd1) A_BOOL_CC_SCALbx10_ARA0(clk, reset, A_BOOL_CC_SCALbx10_ARA0_RDD0, A_BOOL_CC_SCALbx10_ARA0_AD0 , A_BOOL_CC_SCALbx10_ARA0_WEN0, A_BOOL_CC_SCALbx10_ARA0_REN0, A_BOOL_CC_SCALbx10_ARA0_WRD0); // 5 vectors of width 1 // 1 vectors of width 14 // 1 vectors of width 4 // 64 bits in scalar variables // Total state bits in module = 87 bits. // 1 continuously assigned (wire/non-state) bits // cell CV_SP_SSRAM_FL1 count=1 // Total number of leaf cells = 1 endmodule // // LCP delay estimations included: turn off with -vnl-lcp-delay-estimate=disable //HPR L/S (orangepath) auxiliary reports. //KiwiC compilation report //Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 0.2.16p : 24th-November-2016 //29/11/2016 10:06:44 //Cmd line args: /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -kiwic-register-colours=1 -give-backtrace -vnl-resets=synchronous -vnl-roundtrip=disable -kiwic-cil-dump=combined -kiwic-kcode-dump=enable -bevelab-default-pause-mode=bblock -res2-loadstore-port-count=0 -repack-to-roms=enable Primes.exe Kiwi_vb.dll -root=Primes.Main -vnl=Primes.v //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T400::: //: Linear scan colouring done for 0 vregs using 0 pregs // //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T401::: //: Linear scan colouring done for 0 vregs using 0 pregs // //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T402::: //: Linear scan colouring done for 0 vregs using 0 pregs // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation MyMyThreadSafeObjectProvider`1 for prefix My/MyProject/ThreadSafeObjectProvider`1 //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T403::: //: Linear scan colouring done for 0 vregs using 0 pregs // //---------------------------------------------------------- //Report from kiwife virtual to physical register colouring/mapping for thread T404::: //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5005 dt=SINT usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5006 dt=SINT usecount=2 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5007 dt=SINT usecount=1 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5009 dt=SINT usecount=2 // //Allocate phy reg purpose=localvar msg=allocation for thread T404 for V5008 dt=SINT usecount=3 // //: Linear scan colouring done for 5 vregs using 2 pregs // //---------------------------------------------------------- //Report from KiwiC-fe.rpt::: //KiwiC: front end input processing of class or method called KiwiSystem/Kiwi // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor10 // //KiwiC start_thread (or entry point) id=cctor10 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+0 // //KiwiC: front end input processing of class or method called System/BitConverter // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor12 // //KiwiC start_thread (or entry point) id=cctor12 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+1 // //KiwiC: front end input processing of class or method called My/MyProject // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor16 // //KiwiC start_thread (or entry point) id=cctor16 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+2 // //KiwiC: front end input processing of class or method called Primes // //root_walk start thread at a static method (used as an entry point). Method name=.cctor uid=cctor14 // //KiwiC start_thread (or entry point) id=cctor14 // //Root method elaborated: specificf=S_kickoff_collate leftover=1+3 // //KiwiC: front end input processing of class or method called Primes/Main // //root_walk start thread at a static method (used as an entry point). Method name=Main uid=Main10 // //KiwiC start_thread (or entry point) id=Main10 // //Register sharing: general T404/Primes/Printer/0.12/V_1/GP used for T404/Primes/Printer/0.12/V_1 // //Register sharing: general T404/Primes/Printer/0.12/V_1/GP used for T404/Primes/CrossingsOff/0.10/V_1 // //Register sharing: general T404/Primes/Printer/0.12/V_0/GP used for T404/Primes/Printer/0.12/V_0 // //Register sharing: general T404/Primes/Printer/0.12/V_0/GP used for T404/Primes/CrossingsOff/0.10/V_0 // //Register sharing: general T404/Primes/Printer/0.12/V_0/GP used for T404/Primes/Setter/0.8/V_0 // //Root method elaborated: specificf=S_root_method leftover=0+0 // //Report of all settings used from the recipe or command line: // // cil-uwind-budget=10000 // // kiwic-finish=enable // // kiwic-cil-dump=combined // // kiwic-kcode-dump=enable // // kiwic-register-colours=1 // // array-4d-name=KIWIARRAY4D // // array-3d-name=KIWIARRAY3D // // array-2d-name=KIWIARRAY2D // // kiwi-dll=Kiwi.dll // // kiwic-dll=Kiwic.dll // // kiwic-zerolength-arrays=disable // // kiwic-fpgaconsole-default=enable // // postgen-optimise=enable // // kiwife-loglevel=20 // // ataken-loglevel=20 // // gtrace-loglevel=20 // // firstpass-loglevel=20 // // overloads-loglevel=20 // // root=Primes.Main // // ?>?=srcfile, Primes.exe, Kiwi_vb.dll // //END OF KIWIC REPORT FILE // //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation MyMTh$star1$/My/MyProject/MyWebServices/T for prefix My/MyProject/ThreadSafeObjectProvider`1/$star1$/My/MyProject/MyWebServices/T //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation MyMTh$star1$/Microsoft/VisualBasic/ApplicationServices/User/T for prefix My/MyProject/ThreadSafeObjectProvider`1/$star1$/Microsoft/VisualBasic/ApplicationServices/User/T //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation MyMTh$star1$/My/MyComputer/T for prefix My/MyProject/ThreadSafeObjectProvider`1/$star1$/My/MyComputer/T //---------------------------------------------------------- //Report from Abbreviation::: //Setting up abbreviation MyMTh$star1$/My/MyApplication/T for prefix My/MyProject/ThreadSafeObjectProvider`1/$star1$/My/MyApplication/T //---------------------------------------------------------- //Report from restructure2::: //Offchip Load/Store (and other) Ports = Nothing to Report // //---------------------------------------------------------- //Report from restructure2::: //Restructure Technology Settings //*---------------------------+---------+---------------------------------------------------------------------------------* //| Key | Value | Description | //*---------------------------+---------+---------------------------------------------------------------------------------* //| int-flr-mul | -3000 | | //| fp-fl-dp-div | 5 | | //| fp-fl-dp-add | 4 | | //| fp-fl-dp-mul | 3 | | //| fp-fl-sp-div | 5 | | //| fp-fl-sp-add | 4 | | //| fp-fl-sp-mul | 3 | | //| max-no-fp-addsubs | 6 | Maximum number of adders and subtractors (or combos) to instantiate per thread. | //| max-no-fp-muls | 6 | Maximum number of f/p multipliers or dividers to instantiate per thread. | //| max-no-int-muls | 3 | Maximum number of int multipliers to instantiate per thread. | //| max-no-fp-divs | 2 | Maximum number of f/p dividers to instantiate per thread. | //| max-no-int-divs | 2 | Maximum number of int dividers to instantiate per thread. | //| res2-offchip-threshold | 1000000 | | //| res2-combrom-threshold | 64 | | //| res2-combram-threshold | 32 | | //| res2-regfile-threshold | 8 | | //| res2-loadstore-port-count | 0 | | //*---------------------------+---------+---------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for xpc10 //*------------------+-----+-------------+------+------+-------+-----+-------------+------* //| gb-flag/Pause | eno | hwm | root | exec | start | end | antecedants | next | //*------------------+-----+-------------+------+------+-------+-----+-------------+------* //| X0:"0:xpc10" | 900 | hwm=0.0.0 | 0 | 0 | - | - | --- | 1 | //| X1:"1:xpc10" | 901 | hwm=0.0.0 | 1 | 1 | - | - | --- | 2 | //| X2:"2:xpc10" | 903 | hwm=0.0.0 | 2 | 2 | - | - | --- | 4 | //| X2:"2:xpc10" | 902 | hwm=0.0.1 | 2 | 2 | 3 | 3 | --- | 2 | //| X4:"4:xpc10" | 905 | hwm=0.0.0 | 4 | 4 | - | - | --- | 7 | //| X4:"4:xpc10" | 904 | hwm=0.0.0 | 4 | 4 | - | - | --- | 5 | //| X8:"8:xpc10" | 907 | hwm=0.0.0 | 5 | 5 | - | - | --- | 4 | //| X8:"8:xpc10" | 906 | hwm=0.0.1 | 5 | 5 | 6 | 6 | --- | 5 | //| X16:"16:xpc10" | 910 | hwm=1.1.0 | 7 | 8 | - | - | --- | 9 | //| X16:"16:xpc10" | 909 | hwm=1.1.0 | 7 | 8 | - | - | --- | 9 | //| X16:"16:xpc10" | 908 | hwm=1.1.0 | 7 | 8 | - | - | --- | 7 | //| X32:"32:xpc10" | 911 | hwm=0.0.0 | 9 | 9 | - | - | --- | 7 | //*------------------+-----+-------------+------+------+-------+-----+-------------+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X0:"0:xpc10" 900 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X0:"0:xpc10" //res2: Thread=xpc10 state=X0:"0:xpc10" //*-----+-----+---------+--------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+--------------------* //| 0 | - | R0 CTRL | | //| 0 | 900 | R0 DATA | | //| 0+E | 900 | W0 DATA | PLI:Primes Start: | //*-----+-----+---------+--------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X1:"1:xpc10" 901 : major_start_pcl=1 edge_private_start/end=-1/-1 exec=1 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X1:"1:xpc10" //res2: Thread=xpc10 state=X1:"1:xpc10" //*-----+-----+---------+---------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+---------------------------------------------------------------------------* //| 1 | - | R0 CTRL | | //| 1 | 901 | R0 DATA | | //| 1+E | 901 | W0 DATA | T404/Primes/Printer/0.12/V_0_GP te=te:1 scalarw(0) PLI:Setting All Flags | //*-----+-----+---------+---------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"2:xpc10" 903 : major_start_pcl=2 edge_private_start/end=-1/-1 exec=2 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X2:"2:xpc10" 902 : major_start_pcl=2 edge_private_start/end=3/3 exec=2 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X2:"2:xpc10" //res2: Thread=xpc10 state=X2:"2:xpc10" //*-----+-----+---------+-----------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------* //| 2 | - | R0 CTRL | | //| 2 | 902 | R0 DATA | | //| 2+E | 902 | W0 DATA | T404/Primes/Printer/0.12/V_0_GP te=te:2 scalarw(E1) @_BOOL/CC/SCALbx10_ARA0 te=te:2 write(E2, U1'1) | //| 3 | 902 | W1 DATA | | //| 2 | 903 | R0 DATA | | //| 2+E | 903 | W0 DATA | T404/Primes/Printer/0.12/V_0_GP te=te:2 scalarw(2) PLI:Crossings Off Flags | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"4:xpc10" 905 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X4:"4:xpc10" 904 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X4:"4:xpc10" //res2: Thread=xpc10 state=X4:"4:xpc10" //*-----+-----+---------+------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------------------------------------------------------------------------------------------------------------------------------------* //| 4 | - | R0 CTRL | | //| 4 | 904 | R0 DATA | | //| 4+E | 904 | W0 DATA | T404/Primes/Printer/0.12/V_1_GP te=te:4 scalarw(E3) | //| 4 | 905 | R0 DATA | | //| 4+E | 905 | W0 DATA | T404/Primes/Printer/0.12/V_0_GP te=te:4 scalarw(0) T404/Primes/Printer/0.12/V_1_GP te=te:4 scalarw(0) PLI:Printing out the pri... | //*-----+-----+---------+------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 907 : major_start_pcl=5 edge_private_start/end=-1/-1 exec=5 (dend=0) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X8:"8:xpc10" 906 : major_start_pcl=5 edge_private_start/end=6/6 exec=5 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X8:"8:xpc10" //res2: Thread=xpc10 state=X8:"8:xpc10" //*-----+-----+---------+-----------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------* //| 5 | - | R0 CTRL | | //| 5 | 906 | R0 DATA | | //| 5+E | 906 | W0 DATA | @_BOOL/CC/SCALbx10_ARA0 te=te:5 write(E4, U1'0) T404/Primes/Printer/0.12/V_1_GP te=te:5 scalarw(E5) | //| 6 | 906 | W1 DATA | | //| 5 | 907 | R0 DATA | | //| 5+E | 907 | W0 DATA | T404/Primes/Printer/0.12/V_0_GP te=te:5 scalarw(E1) | //*-----+-----+---------+-----------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 910 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=8 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 909 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=8 (dend=1) //, Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X16:"16:xpc10" 908 : major_start_pcl=7 edge_private_start/end=-1/-1 exec=8 (dend=1) //Simple greedy schedule for res2: Thread=xpc10 state=X16:"16:xpc10" //res2: Thread=xpc10 state=X16:"16:xpc10" //*-----+-----+---------+------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+------------------------------------------------------------------------* //| 7 | - | R0 CTRL | @_BOOL/CC/SCALbx10_ARA0 te=te:7 read(E4) | //| 8 | - | R1 CTRL | | //| 7 | 908 | R0 DATA | | //| 8 | 908 | R1 DATA | | //| 8+E | 908 | W0 DATA | PLI:GSAI:hpr_sysexit PLI:Primes End: PLI:There are %u primes ... | //| 7 | 909 | R0 DATA | | //| 8 | 909 | R1 DATA | | //| 8+E | 909 | W0 DATA | T404/Primes/Printer/0.12/V_0_GP te=te:8 scalarw(E1) PLI: %u is prime | //| 7 | 910 | R0 DATA | | //| 8 | 910 | R1 DATA | | //| 8+E | 910 | W0 DATA | | //*-----+-----+---------+------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: Thread=xpc10 state=X32:"32:xpc10" 911 : major_start_pcl=9 edge_private_start/end=-1/-1 exec=9 (dend=0) //Simple greedy schedule for res2: Thread=xpc10 state=X32:"32:xpc10" //res2: Thread=xpc10 state=X32:"32:xpc10" //*-----+-----+---------+-----------------------------------------------------* //| pc | eno | Phaser | Work | //*-----+-----+---------+-----------------------------------------------------* //| 9 | - | R0 CTRL | | //| 9 | 911 | R0 DATA | | //| 9+E | 911 | W0 DATA | T404/Primes/Printer/0.12/V_1_GP te=te:9 scalarw(E6) | //*-----+-----+---------+-----------------------------------------------------* // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // E1 =.= 1+T404/Primes/Printer/0.12/V_0_GP // // E2 =.= T404/Primes/Printer/0.12/V_0_GP // // E3 =.= 2*T404/Primes/Printer/0.12/V_0_GP // // E4 =.= T404/Primes/Printer/0.12/V_1_GP // // E5 =.= T404/Primes/Printer/0.12/V_0_GP+T404/Primes/Printer/0.12/V_1_GP // // E6 =.= 1+T404/Primes/Printer/0.12/V_1_GP // // E7 =.= T404/Primes/Printer/0.12/V_0_GP<S32'10000 // // E8 =.= T404/Primes/Printer/0.12/V_0_GP>=S32'10000 // // E9 =.= T404/Primes/Printer/0.12/V_1_GP<S32'10000 // // E10 =.= T404/Primes/Printer/0.12/V_1_GP>=S32'10000 // // E11 =.= {[T404/Primes/Printer/0.12/V_1_GP<S32'10000, xpc10nz==X8:"8:xpc10nz", |-|@_BOOL/CC/SCALbx10_ARA0_RDD0]; [T404/Primes/Printer/0.12/V_1_GP<S32'10000, xpc10nz!=X8:"8:xpc10nz", |-|BOOLCCSCALbx10ARA0RRh10hold]} // // E12 =.= {[T404/Primes/Printer/0.12/V_1_GP<S32'10000, xpc10nz==X8:"8:xpc10nz", !(|-|@_BOOL/CC/SCALbx10_ARA0_RDD0)]; [T404/Primes/Printer/0.12/V_1_GP<S32'10000, xpc10nz!=X8:"8:xpc10nz", !(|-|BOOLCCSCALbx10ARA0RRh10hold)]} // //---------------------------------------------------------- //Report from verilog_render::: //5 vectors of width 1 // //1 vectors of width 14 // //1 vectors of width 4 // //64 bits in scalar variables // //Total state bits in module = 87 bits. // //1 continuously assigned (wire/non-state) bits // //Total number of leaf cells = 0 // //Major Statistics Report: //Thread .cctor uid=cctor10 has 3 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor12 has 2 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor16 has 9 CIL instructions in 1 basic blocks //Thread .cctor uid=cctor14 has 3 CIL instructions in 1 basic blocks //Thread Main uid=Main10 has 41 CIL instructions in 15 basic blocks //Thread mpc10 has 7 bevelab control states (pauses) //Reindexed thread xpc10 with 10 minor control states // eof (HPR L/S Verilog)