// CBG Orangepath HPR L/S System // Verilog output file generated at 21/01/2016 15:58:23 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 2.01: January-2016 Unix 3.19.8.100 // /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -verilog-roundtrip=disable -report-each-step -kiwic-finish=enable -kiwic-kcode-dump=enable -kiwic-cil-dump=separately -gtrace-loglevel=0 test2r1.exe -vnl-resets=synchronous -vnl DUT.v -sim 180 -give-backtrace -report-each-step `timescale 1ns/10ps module DUT( output hf1_dram0bank_opreq, input hf1_dram0bank_oprdy, input hf1_dram0bank_ack, output hf1_dram0bank_rwbar, output [255:0] hf1_dram0bank_wdata, output [21:0] hf1_dram0bank_addr, input [255:0] hf1_dram0bank_rdata, output [31:0] hf1_dram0bank_lanes, input clk, input reset); wire clk; wire reset; integer tTMT4Main_V_0; integer tTMT4Main_V_1; reg [31:0] tTMT4Main_V_6; integer tTpT4process_V_0; reg [31:0] tTpT4process_V_1; reg signed [31:0] A_SINT_CC_MAPR10NoCE1_capint; reg signed [31:0] A_SINT_CC_MAPR10NoCE0_capint; reg [31:0] A_star1_Capsule_CC_SCALbx16_datum; reg [31:0] A_star1_Capsule_CC_SCALbx18_datum; reg A_BOOL_CC_SCALbx16_emptyflag; reg A_BOOL_CC_SCALbx18_emptyflag; reg A_BOOL_CC_MAPR10NoCE1_newlinef; reg A_BOOL_CC_MAPR10NoCE0_newlinef; reg hprtestandsetres10; reg hprtestandsetres14; reg hprtestandsetres26; reg hprtestandsetres30; wire [31:0] isMULTIPLIER10_RR; reg [31:0] isMULTIPLIER10_NN; reg [31:0] isMULTIPLIER10_DD; wire isMULTIPLIER10_err; wire [31:0] isMULTIPLIER12_RR; reg [31:0] isMULTIPLIER12_NN; reg [31:0] isMULTIPLIER12_DD; wire isMULTIPLIER12_err; reg [4:0] xpc12nz; reg [31:0] isMULTIPLIER12RRh10hold; reg isMULTIPLIER12RRh10shot0; reg isMULTIPLIER12RRh10shot1; reg [31:0] isMULTIPLIER10RRh10hold; reg isMULTIPLIER10RRh10shot0; reg isMULTIPLIER10RRh10shot1; reg [5:0] xpc10nz; always @(* ) begin isMULTIPLIER12_NN = 0; isMULTIPLIER12_DD = 0; isMULTIPLIER10_NN = 0; isMULTIPLIER10_DD = 0; case (xpc10nz) 5'd20/*20:US*/: begin isMULTIPLIER10_DD = tTMT4Main_V_1; isMULTIPLIER10_NN = tTMT4Main_V_0; end 5'd25/*25:US*/: begin isMULTIPLIER12_DD = tTMT4Main_V_1; isMULTIPLIER12_NN = tTMT4Main_V_0; end endcase end always @(posedge clk ) begin //Start structure HPR test2r1.exe if (reset) begin hprtestandsetres26 <= 1'd0; tTpT4process_V_1 <= 32'd0; hprtestandsetres30 <= 1'd0; tTpT4process_V_0 <= 32'd0; xpc12nz <= 5'd0; hprtestandsetres10 <= 1'd0; A_star1_Capsule_CC_SCALbx16_datum <= 32'd0; tTMT4Main_V_0 <= 32'd0; hprtestandsetres14 <= 1'd0; A_star1_Capsule_CC_SCALbx18_datum <= 32'd0; tTMT4Main_V_6 <= 32'd0; tTMT4Main_V_1 <= 32'd0; A_SINT_CC_MAPR10NoCE0_capint <= 32'd0; A_BOOL_CC_MAPR10NoCE0_newlinef <= 1'd0; A_BOOL_CC_SCALbx18_emptyflag <= 1'd0; A_BOOL_CC_SCALbx16_emptyflag <= 1'd0; A_SINT_CC_MAPR10NoCE1_capint <= 32'd0; A_BOOL_CC_MAPR10NoCE1_newlinef <= 1'd0; isMULTIPLIER10RRh10hold <= 32'd0; isMULTIPLIER10RRh10shot1 <= 1'd0; isMULTIPLIER12RRh10hold <= 32'd0; isMULTIPLIER12RRh10shot1 <= 1'd0; isMULTIPLIER12RRh10shot0 <= 1'd0; isMULTIPLIER10RRh10shot0 <= 1'd0; xpc10nz <= 6'd0; end else begin if ((tTpT4process_V_0>=4'd10) && (xpc12nz==4'd14/*14:US*/)) $finish(0); if ((xpc12nz==4'd11/*11:US*/)) begin if ((((A_star1_Capsule_CC_SCALbx18_datum==1'd1/*1:US*/)? A_BOOL_CC_MAPR10NoCE1_newlinef: (A_star1_Capsule_CC_SCALbx18_datum !=0/*0:US*/)) || A_BOOL_CC_MAPR10NoCE0_newlinef && (A_star1_Capsule_CC_SCALbx18_datum==0/*0:US*/)) && !A_BOOL_CC_SCALbx18_emptyflag ) begin $write("%d ", ((A_star1_Capsule_CC_SCALbx18_datum==1'd1/*1:US*/)? A_SINT_CC_MAPR10NoCE1_capint: ((A_star1_Capsule_CC_SCALbx18_datum ==0/*0:US*/)? A_SINT_CC_MAPR10NoCE0_capint: 1'bx))); $display(""); end if ((!A_BOOL_CC_MAPR10NoCE0_newlinef && (A_star1_Capsule_CC_SCALbx18_datum==0/*0:US*/) || !A_BOOL_CC_MAPR10NoCE1_newlinef && (A_star1_Capsule_CC_SCALbx18_datum==1'd1/*1:US*/)) && !A_BOOL_CC_SCALbx18_emptyflag) $write("%d ", ((A_star1_Capsule_CC_SCALbx18_datum ==1'd1/*1:US*/)? A_SINT_CC_MAPR10NoCE1_capint: ((A_star1_Capsule_CC_SCALbx18_datum==0/*0:US*/)? A_SINT_CC_MAPR10NoCE0_capint : 1'bx))); end if (((33'h1ffffffff&32'd3)