// CBG Orangepath HPR L/S System // Verilog output file generated at 09/03/2018 07:41:57 // Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version Alpha 0.3.5k : 1st Mar 2018 Linux/X86_64:koo // /rack-ham/paula1/homedir/home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -vnl-roundtrip=disable -report-each-step -vnl-resets=synchronous -kiwife-directorate-endmode=finish -ip-incdir=/rack-ham/paula1/homedir/home/djg11/d320/hprls/kiwipro/kiwic/src/tinytests:.:/tmp/ip_block_folder1 -res2-share-array-reads=enable -res2-regen-sequencer=enable -res2-extend-schedules-to-keep-pli-order=full test61.exe -sim=1800 -compose=disable -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test61.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=hard -give-backtrace -report-each-step `timescale 1ns/1ns module DUT( /* portgroup= abstractionName=kiwicmiscio10 */ output reg done, output reg [7:0] ksubsAbendSyndrome, output reg [7:0] ksubsGpioLeds, output reg [7:0] ksubsManualWaypoint, /* portgroup= abstractionName=res2-directornets */ output reg [2:0] test6110PC10nz_pc_export, /* portgroup= abstractionName=L2590-vg pi_name=net2batch10 */ input clk, /* portgroup= abstractionName=directorate-vg-dir pi_name=directorate10 */ input reset); function [31:0] rtl_unsigned_extend0; input [7:0] arg; rtl_unsigned_extend0 = { 24'b0, arg[7:0] }; endfunction // abstractionName=kiwicmainnets10 reg [31:0] bench_T404_bench_Main_T404_bench_Main_V_2; reg [31:0] bench_T404_bench_Main_T404_bench_Main_V_1; reg signed [31:0] bench_T404_bench_Main_T404_bench_Main_V_0; // abstractionName=res2-contacts pi_name=SROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1 wire [7:0] i8USCCtally8SCALbx10tally8ARA0mirror10_rdata; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror10_addr; reg i8USCCtally8SCALbx10tally8ARA0mirror10_ren; // abstractionName=res2-contacts pi_name=SROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1 wire [7:0] i8USCCtally8SCALbx10tally8ARA0mirror12_rdata; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror12_addr; reg i8USCCtally8SCALbx10tally8ARA0mirror12_ren; // abstractionName=res2-contacts pi_name=SROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1 wire [7:0] i8USCCtally8SCALbx10tally8ARA0mirror14_rdata; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror14_addr; reg i8USCCtally8SCALbx10tally8ARA0mirror14_ren; // abstractionName=res2-contacts pi_name=SROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1 wire [7:0] i8USCCtally8SCALbx10tally8ARA0mirror16_rdata; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror16_addr; reg i8USCCtally8SCALbx10tally8ARA0mirror16_ren; // abstractionName=res2-morenets reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror16RRh10hold; reg i8USCCtally8SCALbx10tally8ARA0mirror16RRh10shot0; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror14RRh10hold; reg i8USCCtally8SCALbx10tally8ARA0mirror14RRh10shot0; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror12RRh10hold; reg i8USCCtally8SCALbx10tally8ARA0mirror12RRh10shot0; reg [7:0] i8USCCtally8SCALbx10tally8ARA0mirror10RRh10hold; reg i8USCCtally8SCALbx10tally8ARA0mirror10RRh10shot0; reg [2:0] test6110PC10nz; always @(* ) begin i8USCCtally8SCALbx10tally8ARA0mirror16_ren = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror14_ren = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror12_ren = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror10_ren = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror10_addr = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror12_addr = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror14_addr = 32'sd0; i8USCCtally8SCALbx10tally8ARA0mirror16_addr = 32'sd0; case (test6110PC10nz) 32'h1/*1:test6110PC10nz*/: begin i8USCCtally8SCALbx10tally8ARA0mirror16_addr = $unsigned(32'd255&($signed(32'd31*bench_T404_bench_Main_T404_bench_Main_V_0 )>>32'sd24)); i8USCCtally8SCALbx10tally8ARA0mirror14_addr = $unsigned(32'd255&($signed(32'd31*bench_T404_bench_Main_T404_bench_Main_V_0 )>>32'sd16)); i8USCCtally8SCALbx10tally8ARA0mirror12_addr = $unsigned(32'd255&$signed(32'd31*bench_T404_bench_Main_T404_bench_Main_V_0 )); i8USCCtally8SCALbx10tally8ARA0mirror10_addr = $unsigned(32'd255&($signed(32'd31*bench_T404_bench_Main_T404_bench_Main_V_0 )>>32'sd8)); end endcase i8USCCtally8SCALbx10tally8ARA0mirror10_ren = ((32'h1/*1:test6110PC10nz*/==test6110PC10nz)? 32'd1: 32'd0); i8USCCtally8SCALbx10tally8ARA0mirror12_ren = ((32'h1/*1:test6110PC10nz*/==test6110PC10nz)? 32'd1: 32'd0); i8USCCtally8SCALbx10tally8ARA0mirror14_ren = ((32'h1/*1:test6110PC10nz*/==test6110PC10nz)? 32'd1: 32'd0); i8USCCtally8SCALbx10tally8ARA0mirror16_ren = ((32'h1/*1:test6110PC10nz*/==test6110PC10nz)? 32'd1: 32'd0); end always @(posedge clk ) begin //Start structure cvtToVerilogtest61/1.0 if (reset) begin ksubsManualWaypoint <= 32'd0; ksubsGpioLeds <= 32'd0; ksubsAbendSyndrome <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror16_addr = 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror14_addr = 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror12_addr = 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror10_addr = 32'd0; bench_T404_bench_Main_T404_bench_Main_V_2 <= 32'd0; bench_T404_bench_Main_T404_bench_Main_V_1 <= 32'd0; done <= 32'd0; test6110PC10nz <= 32'd0; bench_T404_bench_Main_T404_bench_Main_V_0 <= 32'd0; end else case (test6110PC10nz) 32'h3/*3:test6110PC10nz*/: begin if ((32'sh5f5_e100<32'sd21*bench_T404_bench_Main_T404_bench_Main_V_0)) begin $display(" %1d 03 answers %1d", bench_T404_bench_Main_T404_bench_Main_V_1, bench_T404_bench_Main_T404_bench_Main_V_2 ); $display("Test61 BitTally finished."); end else $display(" %1d 03 answers %1d", bench_T404_bench_Main_T404_bench_Main_V_1, bench_T404_bench_Main_T404_bench_Main_V_2 ); if ((32'sh5f5_e100<32'sd21*bench_T404_bench_Main_T404_bench_Main_V_0)) begin test6110PC10nz <= 32'h4/*4:test6110PC10nz*/; done <= 1'h1; bench_T404_bench_Main_T404_bench_Main_V_0 <= 32'sd21*bench_T404_bench_Main_T404_bench_Main_V_0; end else begin test6110PC10nz <= 32'h1/*1:test6110PC10nz*/; bench_T404_bench_Main_T404_bench_Main_V_0 <= 32'sd21*bench_T404_bench_Main_T404_bench_Main_V_0; end end 32'h2/*2:test6110PC10nz*/: begin test6110PC10nz <= 32'h3/*3:test6110PC10nz*/; bench_T404_bench_Main_T404_bench_Main_V_2 <= rtl_unsigned_extend0(((32'h2/*2:test6110PC10nz*/==test6110PC10nz)? i8USCCtally8SCALbx10tally8ARA0mirror16_rdata : i8USCCtally8SCALbx10tally8ARA0mirror16RRh10hold))+rtl_unsigned_extend0(((32'h2/*2:test6110PC10nz*/==test6110PC10nz )? i8USCCtally8SCALbx10tally8ARA0mirror14_rdata: i8USCCtally8SCALbx10tally8ARA0mirror14RRh10hold))+rtl_unsigned_extend0(((32'h2 /*2:test6110PC10nz*/==test6110PC10nz)? i8USCCtally8SCALbx10tally8ARA0mirror12_rdata: i8USCCtally8SCALbx10tally8ARA0mirror12RRh10hold ))+rtl_unsigned_extend0(((32'h2/*2:test6110PC10nz*/==test6110PC10nz)? i8USCCtally8SCALbx10tally8ARA0mirror10_rdata: i8USCCtally8SCALbx10tally8ARA0mirror10RRh10hold )); bench_T404_bench_Main_T404_bench_Main_V_1 <= $signed(32'd31*bench_T404_bench_Main_T404_bench_Main_V_0); end 32'h1/*1:test6110PC10nz*/: test6110PC10nz <= 32'h2/*2:test6110PC10nz*/; 32'h0/*0:test6110PC10nz*/: begin test6110PC10nz <= 32'h1/*1:test6110PC10nz*/; done <= 1'h0; ksubsManualWaypoint <= 8'h0; ksubsGpioLeds <= 8'h80; ksubsAbendSyndrome <= 8'h80; bench_T404_bench_Main_T404_bench_Main_V_2 <= 32'h0; bench_T404_bench_Main_T404_bench_Main_V_1 <= 32'h0; bench_T404_bench_Main_T404_bench_Main_V_0 <= 32'sd1; $display("%s%1d", "BitTally 1 Limit=", 32'sh5f5_e100); end 32'h4/*4:test6110PC10nz*/: begin test6110PC10nz <= 32'h5/*5:test6110PC10nz*/; $finish(32'sd0); end endcase if (reset) begin test6110PC10nz_pc_export <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror10RRh10hold <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror12RRh10hold <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror14RRh10hold <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror16RRh10hold <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror16RRh10shot0 <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror14RRh10shot0 <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror12RRh10shot0 <= 32'd0; i8USCCtally8SCALbx10tally8ARA0mirror10RRh10shot0 <= 32'd0; end else begin if (i8USCCtally8SCALbx10tally8ARA0mirror16RRh10shot0) i8USCCtally8SCALbx10tally8ARA0mirror16RRh10hold <= i8USCCtally8SCALbx10tally8ARA0mirror16_rdata ; if (i8USCCtally8SCALbx10tally8ARA0mirror14RRh10shot0) i8USCCtally8SCALbx10tally8ARA0mirror14RRh10hold <= i8USCCtally8SCALbx10tally8ARA0mirror14_rdata ; if (i8USCCtally8SCALbx10tally8ARA0mirror12RRh10shot0) i8USCCtally8SCALbx10tally8ARA0mirror12RRh10hold <= i8USCCtally8SCALbx10tally8ARA0mirror12_rdata ; if (i8USCCtally8SCALbx10tally8ARA0mirror10RRh10shot0) i8USCCtally8SCALbx10tally8ARA0mirror10RRh10hold <= i8USCCtally8SCALbx10tally8ARA0mirror10_rdata ; test6110PC10nz_pc_export <= test6110PC10nz; i8USCCtally8SCALbx10tally8ARA0mirror16RRh10shot0 <= (32'h1/*1:test6110PC10nz*/==test6110PC10nz); i8USCCtally8SCALbx10tally8ARA0mirror14RRh10shot0 <= (32'h1/*1:test6110PC10nz*/==test6110PC10nz); i8USCCtally8SCALbx10tally8ARA0mirror12RRh10shot0 <= (32'h1/*1:test6110PC10nz*/==test6110PC10nz); i8USCCtally8SCALbx10tally8ARA0mirror10RRh10shot0 <= (32'h1/*1:test6110PC10nz*/==test6110PC10nz); end //End structure cvtToVerilogtest61/1.0 end SROM_A_8_US_CC_tally8_SCALbx10_tally8_ARA0_FL1 i8USCCtally8SCALbx10tally8ARA0mirror10( .clk(clk), .reset(reset), .rdata(i8USCCtally8SCALbx10tally8ARA0mirror10_rdata ), .addr(i8USCCtally8SCALbx10tally8ARA0mirror10_addr), .ren(i8USCCtally8SCALbx10tally8ARA0mirror10_ren)); SROM_A_8_US_CC_tally8_SCALbx10_tally8_ARA0_FL1 i8USCCtally8SCALbx10tally8ARA0mirror12( .clk(clk), .reset(reset), .rdata(i8USCCtally8SCALbx10tally8ARA0mirror12_rdata ), .addr(i8USCCtally8SCALbx10tally8ARA0mirror12_addr), .ren(i8USCCtally8SCALbx10tally8ARA0mirror12_ren)); SROM_A_8_US_CC_tally8_SCALbx10_tally8_ARA0_FL1 i8USCCtally8SCALbx10tally8ARA0mirror14( .clk(clk), .reset(reset), .rdata(i8USCCtally8SCALbx10tally8ARA0mirror14_rdata ), .addr(i8USCCtally8SCALbx10tally8ARA0mirror14_addr), .ren(i8USCCtally8SCALbx10tally8ARA0mirror14_ren)); SROM_A_8_US_CC_tally8_SCALbx10_tally8_ARA0_FL1 i8USCCtally8SCALbx10tally8ARA0mirror16( .clk(clk), .reset(reset), .rdata(i8USCCtally8SCALbx10tally8ARA0mirror16_rdata ), .addr(i8USCCtally8SCALbx10tally8ARA0mirror16_addr), .ren(i8USCCtally8SCALbx10tally8ARA0mirror16_ren)); // Structural Resource (FU) inventory:// 1 vectors of width 3 // 8 vectors of width 1 // 8 vectors of width 8 // 3 vectors of width 32 // Total state bits in module = 171 bits. // 32 continuously assigned (wire/non-state) bits // cell SROM_A_8_US_CC_tally8_SCALbx10_tally8_ARA0_FL1 count=4 // Total number of leaf cells = 4 endmodule module SROM_A_8_US_CC_tally8_SCALbx10_tally8_ARA0_FL1( /* portgroup= abstractionName=res2-contacts pi_name=CVRAM10 */ output reg [7:0] rdata, input [7:0] addr, input ren, /* portgroup= abstractionName=L2590-vg pi_name=net2batch12 */ input clk, /* portgroup= abstractionName=directorate-vg-dir pi_name=directorate12 */ input reset); // abstractionName=res2-sim-nets pi_name=CVRAM10 reg [7:0] RomData10[255:0]; always @(posedge clk ) begin //Start structure cvtToVerilogSROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1/1.0 if (reset) rdata <= 32'd0; else rdata <= RomData10[addr]; //End structure cvtToVerilogSROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1/1.0 end //Resource=SROM iname=i8USCCtally8SCALbx10tally8ARA0mirror16 256x8 clk=posedge(clk) synchronous/pipeline=1 no_ports=1 hintname=tally8_ used by threads test6110PC10 initial begin //ROM data table: 256 words of 8 bits. RomData10[0] = 8'h0; RomData10[1] = 8'h1; RomData10[2] = 8'h1; RomData10[3] = 8'h2; RomData10[4] = 8'h1; RomData10[5] = 8'h2; RomData10[6] = 8'h2; RomData10[7] = 8'h3; RomData10[8] = 8'h1; RomData10[9] = 8'h2; RomData10[10] = 8'h2; RomData10[11] = 8'h3; RomData10[12] = 8'h2; RomData10[13] = 8'h3; RomData10[14] = 8'h3; RomData10[15] = 8'h4; RomData10[16] = 8'h1; RomData10[17] = 8'h2; RomData10[18] = 8'h2; RomData10[19] = 8'h3; RomData10[20] = 8'h2; RomData10[21] = 8'h3; RomData10[22] = 8'h3; RomData10[23] = 8'h4; RomData10[24] = 8'h2; RomData10[25] = 8'h3; RomData10[26] = 8'h3; RomData10[27] = 8'h4; RomData10[28] = 8'h3; RomData10[29] = 8'h4; RomData10[30] = 8'h4; RomData10[31] = 8'h5; RomData10[32] = 8'h1; RomData10[33] = 8'h2; RomData10[34] = 8'h2; RomData10[35] = 8'h3; RomData10[36] = 8'h2; RomData10[37] = 8'h3; RomData10[38] = 8'h3; RomData10[39] = 8'h4; RomData10[40] = 8'h2; RomData10[41] = 8'h3; RomData10[42] = 8'h3; RomData10[43] = 8'h4; RomData10[44] = 8'h3; RomData10[45] = 8'h4; RomData10[46] = 8'h4; RomData10[47] = 8'h5; RomData10[48] = 8'h2; RomData10[49] = 8'h3; RomData10[50] = 8'h3; RomData10[51] = 8'h4; RomData10[52] = 8'h3; RomData10[53] = 8'h4; RomData10[54] = 8'h4; RomData10[55] = 8'h5; RomData10[56] = 8'h3; RomData10[57] = 8'h4; RomData10[58] = 8'h4; RomData10[59] = 8'h5; RomData10[60] = 8'h4; RomData10[61] = 8'h5; RomData10[62] = 8'h5; RomData10[63] = 8'h6; RomData10[64] = 8'h1; RomData10[65] = 8'h2; RomData10[66] = 8'h2; RomData10[67] = 8'h3; RomData10[68] = 8'h2; RomData10[69] = 8'h3; RomData10[70] = 8'h3; RomData10[71] = 8'h4; RomData10[72] = 8'h2; RomData10[73] = 8'h3; RomData10[74] = 8'h3; RomData10[75] = 8'h4; RomData10[76] = 8'h3; RomData10[77] = 8'h4; RomData10[78] = 8'h4; RomData10[79] = 8'h5; RomData10[80] = 8'h2; RomData10[81] = 8'h3; RomData10[82] = 8'h3; RomData10[83] = 8'h4; RomData10[84] = 8'h3; RomData10[85] = 8'h4; RomData10[86] = 8'h4; RomData10[87] = 8'h5; RomData10[88] = 8'h3; RomData10[89] = 8'h4; RomData10[90] = 8'h4; RomData10[91] = 8'h5; RomData10[92] = 8'h4; RomData10[93] = 8'h5; RomData10[94] = 8'h5; RomData10[95] = 8'h6; RomData10[96] = 8'h2; RomData10[97] = 8'h3; RomData10[98] = 8'h3; RomData10[99] = 8'h4; RomData10[100] = 8'h3; RomData10[101] = 8'h4; RomData10[102] = 8'h4; RomData10[103] = 8'h5; RomData10[104] = 8'h3; RomData10[105] = 8'h4; RomData10[106] = 8'h4; RomData10[107] = 8'h5; RomData10[108] = 8'h4; RomData10[109] = 8'h5; RomData10[110] = 8'h5; RomData10[111] = 8'h6; RomData10[112] = 8'h3; RomData10[113] = 8'h4; RomData10[114] = 8'h4; RomData10[115] = 8'h5; RomData10[116] = 8'h4; RomData10[117] = 8'h5; RomData10[118] = 8'h5; RomData10[119] = 8'h6; RomData10[120] = 8'h4; RomData10[121] = 8'h5; RomData10[122] = 8'h5; RomData10[123] = 8'h6; RomData10[124] = 8'h5; RomData10[125] = 8'h6; RomData10[126] = 8'h6; RomData10[127] = 8'h7; RomData10[128] = 8'h1; RomData10[129] = 8'h2; RomData10[130] = 8'h2; RomData10[131] = 8'h3; RomData10[132] = 8'h2; RomData10[133] = 8'h3; RomData10[134] = 8'h3; RomData10[135] = 8'h4; RomData10[136] = 8'h2; RomData10[137] = 8'h3; RomData10[138] = 8'h3; RomData10[139] = 8'h4; RomData10[140] = 8'h3; RomData10[141] = 8'h4; RomData10[142] = 8'h4; RomData10[143] = 8'h5; RomData10[144] = 8'h2; RomData10[145] = 8'h3; RomData10[146] = 8'h3; RomData10[147] = 8'h4; RomData10[148] = 8'h3; RomData10[149] = 8'h4; RomData10[150] = 8'h4; RomData10[151] = 8'h5; RomData10[152] = 8'h3; RomData10[153] = 8'h4; RomData10[154] = 8'h4; RomData10[155] = 8'h5; RomData10[156] = 8'h4; RomData10[157] = 8'h5; RomData10[158] = 8'h5; RomData10[159] = 8'h6; RomData10[160] = 8'h2; RomData10[161] = 8'h3; RomData10[162] = 8'h3; RomData10[163] = 8'h4; RomData10[164] = 8'h3; RomData10[165] = 8'h4; RomData10[166] = 8'h4; RomData10[167] = 8'h5; RomData10[168] = 8'h3; RomData10[169] = 8'h4; RomData10[170] = 8'h4; RomData10[171] = 8'h5; RomData10[172] = 8'h4; RomData10[173] = 8'h5; RomData10[174] = 8'h5; RomData10[175] = 8'h6; RomData10[176] = 8'h3; RomData10[177] = 8'h4; RomData10[178] = 8'h4; RomData10[179] = 8'h5; RomData10[180] = 8'h4; RomData10[181] = 8'h5; RomData10[182] = 8'h5; RomData10[183] = 8'h6; RomData10[184] = 8'h4; RomData10[185] = 8'h5; RomData10[186] = 8'h5; RomData10[187] = 8'h6; RomData10[188] = 8'h5; RomData10[189] = 8'h6; RomData10[190] = 8'h6; RomData10[191] = 8'h7; RomData10[192] = 8'h2; RomData10[193] = 8'h3; RomData10[194] = 8'h3; RomData10[195] = 8'h4; RomData10[196] = 8'h3; RomData10[197] = 8'h4; RomData10[198] = 8'h4; RomData10[199] = 8'h5; RomData10[200] = 8'h3; RomData10[201] = 8'h4; RomData10[202] = 8'h4; RomData10[203] = 8'h5; RomData10[204] = 8'h4; RomData10[205] = 8'h5; RomData10[206] = 8'h5; RomData10[207] = 8'h6; RomData10[208] = 8'h3; RomData10[209] = 8'h4; RomData10[210] = 8'h4; RomData10[211] = 8'h5; RomData10[212] = 8'h4; RomData10[213] = 8'h5; RomData10[214] = 8'h5; RomData10[215] = 8'h6; RomData10[216] = 8'h4; RomData10[217] = 8'h5; RomData10[218] = 8'h5; RomData10[219] = 8'h6; RomData10[220] = 8'h5; RomData10[221] = 8'h6; RomData10[222] = 8'h6; RomData10[223] = 8'h7; RomData10[224] = 8'h3; RomData10[225] = 8'h4; RomData10[226] = 8'h4; RomData10[227] = 8'h5; RomData10[228] = 8'h4; RomData10[229] = 8'h5; RomData10[230] = 8'h5; RomData10[231] = 8'h6; RomData10[232] = 8'h4; RomData10[233] = 8'h5; RomData10[234] = 8'h5; RomData10[235] = 8'h6; RomData10[236] = 8'h5; RomData10[237] = 8'h6; RomData10[238] = 8'h6; RomData10[239] = 8'h7; RomData10[240] = 8'h4; RomData10[241] = 8'h5; RomData10[242] = 8'h5; RomData10[243] = 8'h6; RomData10[244] = 8'h5; RomData10[245] = 8'h6; RomData10[246] = 8'h6; RomData10[247] = 8'h7; RomData10[248] = 8'h5; RomData10[249] = 8'h6; RomData10[250] = 8'h6; RomData10[251] = 8'h7; RomData10[252] = 8'h6; RomData10[253] = 8'h7; RomData10[254] = 8'h7; RomData10[255] = 8'h8; end // Structural Resource (FU) inventory:// 256 array locations of width 8 // Total state bits in module = 2048 bits. // Total number of leaf cells = 0 endmodule // // Layout wiring length esimtation mode is LAYOUT_lcp. //HPR L/S (orangepath) auxiliary reports. //KiwiC compilation report //Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version Alpha 0.3.5k : 1st Mar 2018 //09/03/2018 07:41:52 //Cmd line args: /rack-ham/paula1/homedir/home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -vnl-roundtrip=disable -report-each-step -vnl-resets=synchronous -kiwife-directorate-endmode=finish -ip-incdir=/rack-ham/paula1/homedir/home/djg11/d320/hprls/kiwipro/kiwic/src/tinytests:.:/tmp/ip_block_folder1 -res2-share-array-reads=enable -res2-regen-sequencer=enable -res2-extend-schedules-to-keep-pli-order=full test61.exe -sim=1800 -compose=disable -vnl-rootmodname=DUT -vnl-resets=synchronous -vnl=test61.v -res2-loadstore-port-count=0 -bevelab-default-pause-mode=hard -give-backtrace -report-each-step //---------------------------------------------------------- //Report from Abbreviation::: // setting up abbreviation @8 for prefix @/8 // //---------------------------------------------------------- //Report from KiwiC-fe.rpt::: //KiwiC: front end input processing of class or method called KiwiSystem.Kiwi // //root_walk start thread at a static method (used as an entry point). Method name=KiwiSystem/Kiwi/.cctor uid=cctor16 // //KiwiC start_thread (or entry point) uid=cctor16 full_idl=KiwiSystem.Kiwi..cctor // //Root method elaborated: specificf=S_kickoff_collate leftover=1+0 // //KiwiC: front end input processing of class or method called System.BitConverter // //root_walk start thread at a static method (used as an entry point). Method name=System/BitConverter/.cctor uid=cctor14 // //KiwiC start_thread (or entry point) uid=cctor14 full_idl=System.BitConverter..cctor // //Root method elaborated: specificf=S_kickoff_collate leftover=1+1 // //KiwiC: front end input processing of class or method called bench // //root_walk start thread at a static method (used as an entry point). Method name=bench/.cctor uid=cctor12 // //KiwiC start_thread (or entry point) uid=cctor12 full_idl=bench..cctor // //Root method elaborated: specificf=S_kickoff_collate leftover=1+2 // //KiwiC: front end input processing of class or method called BitTally // //root_walk start thread at a static method (used as an entry point). Method name=BitTally/.cctor uid=cctor10 // //KiwiC start_thread (or entry point) uid=cctor10 full_idl=BitTally..cctor // //Root method elaborated: specificf=S_kickoff_collate leftover=1+3 // //KiwiC: front end input processing of class or method called bench // //root_compiler: start elaborating class 'bench' // //elaborating class 'bench' // //compiling static method as entry point: style=Root idl=bench/Main // //Performing root elaboration of method bench.Main // //KiwiC start_thread (or entry point) uid=Main10 full_idl=bench.Main // //root_compiler class done: bench // //Report of all settings used from the recipe or command line: // // kiwife-directorate-ready-flag=absent // // kiwife-directorate-endmode=finish // // kiwife-directorate-startmode=self-start // // cil-uwind-budget=10000 // // kiwic-cil-dump=disable // // kiwic-kcode-dump=disable // // kiwic-register-colours=disable // // array-4d-name=KIWIARRAY4D // // array-3d-name=KIWIARRAY3D // // array-2d-name=KIWIARRAY2D // // kiwi-dll=Kiwi.dll // // kiwic-dll=Kiwic.dll // // kiwic-zerolength-arrays=disable // // kiwifefpgaconsole-default=enable // // kiwife-directorate-style=basic // // postgen-optimise=enable // // kiwife-cil-loglevel=20 // // kiwife-ataken-loglevel=20 // // kiwife-gtrace-loglevel=20 // // kiwife-firstpass-loglevel=20 // // kiwife-overloads-loglevel=20 // // root=$attributeroot // // srcfile=test61.exe // // kiwic-autodispose=disable // //END OF KIWIC REPORT FILE // //---------------------------------------------------------- //Report from restructure2::: //Offchip Load/Store (and other) Ports = Nothing to Report // //---------------------------------------------------------- //Report from restructure2::: //Restructure Technology Settings //*---------------------------+---------+---------------------------------------------------------------------------------* //| Key | Value | Description | //*---------------------------+---------+---------------------------------------------------------------------------------* //| int-flr-mul | 1000 | | //| max-no-fp-addsubs | 6 | Maximum number of adders and subtractors (or combos) to instantiate per thread. | //| max-no-fp-muls | 6 | Maximum number of f/p multipliers or dividers to instantiate per thread. | //| max-no-int-muls | 3 | Maximum number of int multipliers to instantiate per thread. | //| max-no-fp-divs | 2 | Maximum number of f/p dividers to instantiate per thread. | //| max-no-int-divs | 2 | Maximum number of int dividers to instantiate per thread. | //| max-no-rom-mirrors | 8 | Maximum number of times to mirror a ROM per thread. | //| max-ram-data_packing | 8 | Maximum number of user words to pack into one RAM/loadstore word line. | //| fp-fl-dp-div | 5 | | //| fp-fl-dp-add | 4 | | //| fp-fl-dp-mul | 3 | | //| fp-fl-sp-div | 15 | | //| fp-fl-sp-add | 4 | | //| fp-fl-sp-mul | 5 | | //| res2-offchip-threshold | 1000000 | | //| res2-combrom-threshold | 64 | | //| res2-combram-threshold | 32 | | //| res2-regfile-threshold | 8 | | //| res2-loadstore-port-count | 0 | | //*---------------------------+---------+---------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: //PC codings points for test6110PC10 //*-------------------------+-----+---------+-------------+------+--------+-------+-----+------* //| gb-flag/Pause | eno | Root Pc | hwm | Exec | Reverb | Start | End | Next | //*-------------------------+-----+---------+-------------+------+--------+-------+-----+------* //| XU32'0:"0:test6110PC10" | 809 | 0 | hwm=0.0.0 | 0 | | - | - | 1 | //| XU32'1:"1:test6110PC10" | 808 | 1 | hwm=0.1.0 | 2 | | 2 | 2 | 3 | //| XU32'2:"2:test6110PC10" | 806 | 3 | hwm=0.0.0 | 3 | | - | - | 1 | //| XU32'2:"2:test6110PC10" | 807 | 3 | hwm=0.0.0 | 3 | | - | - | 4 | //| XU32'4:"4:test6110PC10" | 805 | 4 | hwm=0.0.0 | 4 | | - | - | - | //*-------------------------+-----+---------+-------------+------+--------+-------+-----+------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: nopipeline: Thread=test6110PC10 state=XU32'0:"0:test6110PC10" 809 : major_start_pcl=0 edge_private_start/end=-1/-1 exec=0 (dend=0) //Simple greedy schedule for res2: nopipeline: Thread=test6110PC10 state=XU32'0:"0:test6110PC10" //res2: nopipeline: Thread=test6110PC10 state=XU32'0:"0:test6110PC10" //*------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------* //| F0 | - | R0 CTRL | | //| F0 | 809 | R0 DATA | | //| F0+E | 809 | W0 DATA | bench.T404.bench.Main.T404.bench.Main.V_0 te=te:F0 write(1) bench.T404.bench.Main.T404.bench.Main.V_1 te=te:F0 write(U32'0) bench.T404.bench.Main.T404.bench.\ | //| | | | Main.V_2 te=te:F0 write(U32'0) ksubsAbendSyndrome te=te:F0 write(U8'128) ksubsGpioLeds te=te:F0 write(U8'128) ksubsManualWaypoint te=te:F0 write(U8'0) done t\ | //| | | | e=te:F0 write(U1'0) PLI:BitTally 1 Limit= | //*------+-----+---------+----------------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: nopipeline: Thread=test6110PC10 state=XU32'1:"1:test6110PC10" 808 : major_start_pcl=1 edge_private_start/end=2/2 exec=2 (dend=1) //Simple greedy schedule for res2: nopipeline: Thread=test6110PC10 state=XU32'1:"1:test6110PC10" //res2: nopipeline: Thread=test6110PC10 state=XU32'1:"1:test6110PC10" //*------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------* //| F1 | - | R0 CTRL | | //| F1 | 808 | R0 DATA | i8USCCtally8SCALbx10tally8ARA0mirror16 te=te:F1 read(E1) i8USCCtally8SCALbx10tally8ARA0mirror14 te=te:F1 read(E2) i8USCCtally8SCALbx10tally8ARA0mirror\ | //| | | | 12 te=te:F1 read(E3) i8USCCtally8SCALbx10tally8ARA0mirror10 te=te:F1 read(E4) | //| F2 | 808 | R1 DATA | | //| F2+E | 808 | W0 DATA | bench.T404.bench.Main.T404.bench.Main.V_1 te=te:F2 write(E5) bench.T404.bench.Main.T404.bench.Main.V_2 te=te:F2 write(E6) | //*------+-----+---------+---------------------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: nopipeline: Thread=test6110PC10 state=XU32'2:"2:test6110PC10" 806 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //, Absolute key numbers for scheduled edge res2: nopipeline: Thread=test6110PC10 state=XU32'2:"2:test6110PC10" 807 : major_start_pcl=3 edge_private_start/end=-1/-1 exec=3 (dend=0) //Simple greedy schedule for res2: nopipeline: Thread=test6110PC10 state=XU32'2:"2:test6110PC10" //res2: nopipeline: Thread=test6110PC10 state=XU32'2:"2:test6110PC10" //*------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------* //| F3 | - | R0 CTRL | | //| F3 | 807 | R0 DATA | | //| F3+E | 807 | W0 DATA | bench.T404.bench.Main.T404.bench.Main.V_0 te=te:F3 write(E7) done te=te:F3 write(U1'1) PLI:Test61 BitTally fini... PLI: %u 03 answers %u | //| F3 | 806 | R0 DATA | | //| F3+E | 806 | W0 DATA | bench.T404.bench.Main.T404.bench.Main.V_0 te=te:F3 write(E7) PLI: %u 03 answers %u | //*------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------* // //---------------------------------------------------------- //Report from restructure2::: // Absolute key numbers for scheduled edge res2: nopipeline: Thread=test6110PC10 state=XU32'4:"4:test6110PC10" 805 : major_start_pcl=4 edge_private_start/end=-1/-1 exec=4 (dend=0) //Simple greedy schedule for res2: nopipeline: Thread=test6110PC10 state=XU32'4:"4:test6110PC10" //res2: nopipeline: Thread=test6110PC10 state=XU32'4:"4:test6110PC10" //*------+-----+---------+-----------------------* //| pc | eno | Phaser | Work | //*------+-----+---------+-----------------------* //| F4 | - | R0 CTRL | | //| F4 | 805 | R0 DATA | | //| F4+E | 805 | W0 DATA | PLI:GSAI:hpr_sysexit | //*------+-----+---------+-----------------------* // //---------------------------------------------------------- //Report from enumbers::: //Concise expression alias report. // // E1 =.= CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))>>>24) // // E2 =.= CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))>>>16) // // E3 =.= CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))) // // E4 =.= CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))>>>8) // // E5 =.= Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0) // // E6 =.= @8_US/CC/tally8__SCALbx10_tally8__ARA0[CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))>>>8)]+@8_US/CC/tally8__SCALbx10_tally8__ARA0[CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0)))]+@8_US/CC/tally8__SCALbx10_tally8__ARA0[CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))>>>16)]+@8_US/CC/tally8__SCALbx10_tally8__ARA0[CVT(Cu)(255&(Cu(31*bench.T404.bench.Main.T404.bench.Main.V_0))>>>24)] // // E7 =.= 21*bench.T404.bench.Main.T404.bench.Main.V_0 // // E8 =.= S32'100000000<21*bench.T404.bench.Main.T404.bench.Main.V_0 // // E9 =.= S32'100000000>=21*bench.T404.bench.Main.T404.bench.Main.V_0 // //---------------------------------------------------------- //Report from IP-XACT input/output::: //Write IP-XACT component file for test61 to test61 //---------------------------------------------------------- //Report from IP-XACT input/output::: //Write IP-XACT component file for test61SROM_@8_US/CC/tally8__SCALbx10_tally8__ARA0_FL1 to test61SROM_@8_US_CC_tally8__SCALbx10_tally8__ARA0_FL1 //---------------------------------------------------------- //Report from verilog_render::: //Structural Resource (FU) inventory: //1 vectors of width 3 // //8 vectors of width 1 // //8 vectors of width 8 // //3 vectors of width 32 // //Total state bits in module = 171 bits. // //32 continuously assigned (wire/non-state) bits // //Total number of leaf cells = 0 // //---------------------------------------------------------- //Report from verilog_render::: //Structural Resource (FU) inventory: //256 array locations of width 8 // //Total state bits in module = 2048 bits. // //Total number of leaf cells = 0 // //Major Statistics Report: //Thread KiwiSystem/Kiwi/.cctor uid=cctor16 has 6 CIL instructions in 1 basic blocks //Thread System/BitConverter/.cctor uid=cctor14 has 2 CIL instructions in 1 basic blocks //Thread bench/.cctor uid=cctor12 has 2 CIL instructions in 1 basic blocks //Thread BitTally/.cctor uid=cctor10 has 8 CIL instructions in 1 basic blocks //Thread bench/Main uid=Main10 has 27 CIL instructions in 4 basic blocks //Thread mpc10 has 4 bevelab control states (pauses) //Reindexed thread test6110PC10 with 5 minor control states // eof (HPR L/S Verilog)