// CBG Orangepath HPR L/S System

// Verilog output file generated at 12/02/2017 22:50:03
// Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 0.3.1 : 7th-Feb-2017 Unix 3.19.8.100
//  /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -print-limit=20 -kiwic-register-colours=1 -vnl-resets=asynchronous -vnl-roundtrip=disable -kiwic-kcode-dump=enable -bevelab-default-pause-mode=hard -bevelab-soft-pause-threshold=150 -kiwic-autodispose=enable -res2-loadstore-port-count=0 -vnl-rootmodname DUT bittally.exe -vnl bittally.v
`timescale 1ns/1ns


module DUT(output reg done, input clk, input reset);

function [31:0] rtl_unsigned_bitextract0;
   input [63:0] arg;
   rtl_unsigned_bitextract0 = $unsigned(arg[31:0]);
   endfunction

  integer bench_T404_Main_T404_Main_V_0;
  reg [1:0] xpc10nz;
 always   @(posedge clk or posedge reset )  begin 
      //Start structure HPR bittally
      if (reset)  begin 
               done <= 32'd0;
               bench_T404_Main_T404_Main_V_0 <= 32'd0;
               xpc10nz <= 32'd0;
               end 
               else 
          case (xpc10nz)
              32'sd0/*0:xpc10nz*/:  begin 
                  $display("%s%1d", "BitTally 02 Limit=", 32'sh5f5_e100);
                   done <= 1'h0;
                   bench_T404_Main_T404_Main_V_0 <= 2'sd1;
                   xpc10nz <= 2'sd1/*1:xpc10nz*/;
                   end 
                  
              2'sd1/*1:xpc10nz*/:  begin 
                  $display("   value=%H  has %1d ones (decimal).", $signed(32'd51*bench_T404_Main_T404_Main_V_0), (rtl_unsigned_bitextract0(32'sh101_0101
                  *(32'shf0f_0f0f&$unsigned((32'sh_3333_3333&($unsigned($signed(32'd51*bench_T404_Main_T404_Main_V_0)+(0-(32'sh_5555_5555
                  &($signed(32'd51*bench_T404_Main_T404_Main_V_0)>>2'sd1))))>>2'sd2))+(32'sh_3333_3333&$unsigned($signed(32'd51*bench_T404_Main_T404_Main_V_0
                  )+(0-(32'sh_5555_5555&($signed(32'd51*bench_T404_Main_T404_Main_V_0)>>2'sd1))))))+($unsigned((32'sh_3333_3333&($unsigned($signed(32'd51
                  *bench_T404_Main_T404_Main_V_0)+(0-(32'sh_5555_5555&($signed(32'd51*bench_T404_Main_T404_Main_V_0)>>2'sd1))))>>2'sd2
                  ))+(32'sh_3333_3333&$unsigned($signed(32'd51*bench_T404_Main_T404_Main_V_0)+(0-(32'sh_5555_5555&($signed(32'd51*bench_T404_Main_T404_Main_V_0
                  )>>2'sd1))))))>>32'sd4)))>>32'sd24));
                  if ((32'sh5f5_e100<32'sd21*bench_T404_Main_T404_Main_V_0)) $display(" Test BitTally finished.");
                      if ((32'sh5f5_e100<32'sd21*bench_T404_Main_T404_Main_V_0))  begin 
                           done <= 1'h1;
                           bench_T404_Main_T404_Main_V_0 <= 32'sd21*bench_T404_Main_T404_Main_V_0;
                           xpc10nz <= 2'sd2/*2:xpc10nz*/;
                           end 
                           else  begin 
                           bench_T404_Main_T404_Main_V_0 <= 32'sd21*bench_T404_Main_T404_Main_V_0;
                           xpc10nz <= 2'sd1/*1:xpc10nz*/;
                           end 
                           end 
                  
              2'sd2/*2:xpc10nz*/:  begin 
                  $finish(32'sd0);
                   xpc10nz <= 2'sd2/*2:xpc10nz*/;
                   end 
                  endcase
      //End structure HPR bittally


       end 
      

// 1 vectors of width 2
// 32 bits in scalar variables
// Total state bits in module = 34 bits.
// Total number of leaf cells = 0
endmodule