// CBG Orangepath HPR L/S System

// Verilog output file generated at 12/02/2017 22:32:47
// Kiwi Scientific Acceleration (KiwiC .net/CIL/C# to Verilog/SystemC compiler): Version alpha 0.3.1 : 7th-Feb-2017 Unix 3.19.8.100
//  /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/kiwic.exe -print-limit=20 -kiwic-register-colours=1 -vnl-resets=asynchronous -vnl-roundtrip=disable -kiwic-kcode-dump=enable -bevelab-default-pause-mode=hard -bevelab-soft-pause-threshold=150 -kiwic-autodispose=enable -res2-loadstore-port-count=0 -vnl-rootmodname DUT bittally.exe -vnl bittally.v
`timescale 1ns/1ns


module DUT(output reg done, input clk, input reset);

function [31:0] rtl_unsigned_extend0;
   input [1:0] arg;
   rtl_unsigned_extend0 = { 30'b0, arg[1:0] };
   endfunction

  integer bench_T403_Main_T403_Main_V_0;
  reg [1:0] xpc10nz;
  wire [31:0] hprpin500075x10;
  wire [31:0] hprpin500087x10;
  wire [31:0] hprpin500099x10;
  wire [31:0] hprpin500111x10;
  wire [31:0] hprpin500123x10;
  wire [31:0] hprpin500135x10;
  wire [31:0] hprpin500147x10;
  wire [31:0] hprpin500159x10;
  wire [31:0] hprpin500171x10;
  wire [31:0] hprpin500183x10;
  wire [31:0] hprpin500195x10;
  wire [31:0] hprpin500207x10;
  wire [31:0] hprpin500219x10;
  wire [31:0] hprpin500231x10;
  wire [31:0] hprpin500243x10;
 always   @(posedge clk or posedge reset )  begin 
      //Start structure HPR bittally
      if (reset)  begin 
               done <= 32'd0;
               bench_T403_Main_T403_Main_V_0 <= 32'd0;
               xpc10nz <= 32'd0;
               end 
               else 
          case (xpc10nz)
              32'sd0/*0:xpc10nz*/:  begin 
                  $display("%s%1d", "BitTally 00 Limit=", 32'sh5f5_e100);
                   done <= 1'h0;
                   bench_T403_Main_T403_Main_V_0 <= 2'sd1;
                   xpc10nz <= 2'sd1/*1:xpc10nz*/;
                   end 
                  
              2'sd1/*1:xpc10nz*/:  begin 
                  $display("   value=%H  has %1d ones (decimal).", $signed(32'd51*bench_T403_Main_T403_Main_V_0), $unsigned((2'sd1&($signed(32'd51
                  *bench_T403_Main_T403_Main_V_0)>>32'sd31)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
                  )>>32'sd30)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500243x10): hprpin500243x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
                  )>>32'sd30)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500243x10): hprpin500243x10))));
                  if ((32'sh5f5_e100<32'sd21*bench_T403_Main_T403_Main_V_0)) $display(" Test BitTally finished.");
                      if ((32'sh5f5_e100<32'sd21*bench_T403_Main_T403_Main_V_0))  begin 
                           done <= 1'h1;
                           bench_T403_Main_T403_Main_V_0 <= 32'sd21*bench_T403_Main_T403_Main_V_0;
                           xpc10nz <= 2'sd2/*2:xpc10nz*/;
                           end 
                           else  begin 
                           bench_T403_Main_T403_Main_V_0 <= 32'sd21*bench_T403_Main_T403_Main_V_0;
                           xpc10nz <= 2'sd1/*1:xpc10nz*/;
                           end 
                           end 
                  
              2'sd2/*2:xpc10nz*/:  begin 
                  $finish(32'sd0);
                   xpc10nz <= 2'sd2/*2:xpc10nz*/;
                   end 
                  endcase
      //End structure HPR bittally


       end 
      

assign hprpin500075x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>2'sd1)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&$signed(32'd51*bench_T403_Main_T403_Main_V_0
)? 32'h1: 32'h0)): (2'sd1&$signed(32'd51*bench_T403_Main_T403_Main_V_0)? 32'h1: 32'h0));

assign hprpin500087x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd3)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>2'sd2)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500075x10): hprpin500075x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>2'sd2)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500075x10): hprpin500075x10));

assign hprpin500099x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd5)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd4)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500087x10): hprpin500087x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd4)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500087x10): hprpin500087x10));

assign hprpin500111x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd7)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd6)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500099x10): hprpin500099x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd6)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500099x10): hprpin500099x10));

assign hprpin500123x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd9)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd8)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500111x10): hprpin500111x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd8)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500111x10): hprpin500111x10));

assign hprpin500135x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd11)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd10)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500123x10): hprpin500123x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd10)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500123x10): hprpin500123x10));

assign hprpin500147x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd13)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd12)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500135x10): hprpin500135x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd12)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500135x10): hprpin500135x10));

assign hprpin500159x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd15)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd14)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500147x10): hprpin500147x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd14)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500147x10): hprpin500147x10));

assign hprpin500171x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd17)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd16)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500159x10): hprpin500159x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd16)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500159x10): hprpin500159x10));

assign hprpin500183x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd19)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd18)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500171x10): hprpin500171x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd18)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500171x10): hprpin500171x10));

assign hprpin500195x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd21)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd20)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500183x10): hprpin500183x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd20)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500183x10): hprpin500183x10));

assign hprpin500207x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd23)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd22)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500195x10): hprpin500195x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd22)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500195x10): hprpin500195x10));

assign hprpin500219x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd25)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd24)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500207x10): hprpin500207x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd24)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500207x10): hprpin500207x10));

assign hprpin500231x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd27)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd26)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500219x10): hprpin500219x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd26)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500219x10): hprpin500219x10));

assign hprpin500243x10 = (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0)>>32'sd29)? $unsigned(rtl_unsigned_extend0(2'sd1)+(2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd28)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500231x10): hprpin500231x10)): (2'sd1&($signed(32'd51*bench_T403_Main_T403_Main_V_0
)>>32'sd28)? $unsigned(rtl_unsigned_extend0(2'sd1)+hprpin500231x10): hprpin500231x10));

// 1 vectors of width 2
// 32 bits in scalar variables
// Total state bits in module = 34 bits.
// 480 continuously assigned (wire/non-state) bits 
// Total number of leaf cells = 0
endmodule