Hazards From Array Memories

A structural hazard in an RTL design can make it non synthesisable.

Consider the following expressions:

Structural hazard sources are numbered: always @(posedge clk) begin q0 <= Boz[e3] // 3 q1 <= Foo[e0] + Foo[e1]; // 1 q2 <= Bar[Bar[e2]]; // 2 q3 <= a*b + c*d; // 4 q4 <= Boz[e4] // 3 end

The RAMs or register files Foo Bar and Boz might not have two read ports. Even with two ports, can Bar perform the double subscription in one clock cycle? Read operations on Boz might be a long way apart in the code, so hazard is hard to spot. The cost of providing two `flash' multipliers for use in one clock cycle while they lie idle much of the rest of the time is likely not warranted.

»KiwiC Structural Hazard Example