** CBG pic14 assembler job tests/cantest.S 1 ; *********************************************** 2 ; * 8pincan.asm * 3 ; * Revision 1.0 September 2000 * 4 ; * Developed by Rick Stoneking * 5 ; * Developed using MPLAB V4.12 and MPASM V2.3 * 6 ; * * 7 ; * This code demonstrates how a very low cost * 8 ; * CAN node can be implemented using a * 9 ; * Microchip PIC12C672 8 pin microcontroller * 10 ; * and a Microchip MCP2510 Stand Alone CAN * 11 ; * controller. * 12 ; * * 13 ; *********************************************** 14 15 ; *********************************************** 16 ; * Setup the MPASM assembler options * 17 ; *********************************************** 18 19 ;; LIST p=12C672 20 21 22 ; *********************************************** 23 ; * Include the standard PIC12C672 include file * 24 ; * and the custom MCP2510 support files * 25 ; *********************************************** 26 27 28 29 include "tests/mcp2510.inc" 30 ;********************************************************************** 31 ; * CAN MCP2510 definitions file * 32 ; ********************************************************************* 33 ; * Filename: MCP2510.inc * 34 ; * Date: 02 Month 1999 * 35 ; * File Version: 0.90 (Beta) * 36 ; ********************************************************************* 37 ; * Functions: * 38 ; * Header file * 39 ; ********************************************************************* 40 ; * Revision History: * 41 ; ********************************************************************* 42 ; 43 ; 44 ;********************************************************************** 45 ; * Register Definitions * 46 ; ********************************************************************* 47 48 ; Configuration Registers * 49 CANSTAT EQU 0x0E 50 CANCTRL EQU 0x0F 51 BFPCTRL EQU 0x0C 52 TEC EQU 0x1C 53 REC EQU 0x1D 54 CNF3 EQU 0x28 55 CNF2 EQU 0x29 56 CNF1 EQU 0x2A 57 CANINTE EQU 0x2B 58 CANINTF EQU 0x2C 59 EFLG EQU 0x2D 60 TXRTSCTRL EQU 0x0D 61 62 ; Receive Filters * 63 RXF0SIDH EQU 0x00 64 RXF0SIDL EQU 0x01 65 RXF0EID8 EQU 0x02 66 RXF0EID0 EQU 0x03 67 RXF1SIDH EQU 0x04 68 RXF1SIDL EQU 0x05 69 RXF1EID8 EQU 0x06 70 RXF1EID0 EQU 0x07 71 RXF2SIDH EQU 0x08 72 RXF2SIDL EQU 0x09 73 RXF2EID8 EQU 0x0A 74 RXF2EID0 EQU 0x0B 75 RXF3SIDH EQU 0x10 76 RXF3SIDL EQU 0x11 77 RXF3EID8 EQU 0x12 78 RXF3EID0 EQU 0x13 79 RXF4SIDH EQU 0x14 80 RXF4SIDL EQU 0x15 81 RXF4EID8 EQU 0x16 82 RXF4EID0 EQU 0x17 83 RXF5SIDH EQU 0x18 84 RXF5SIDL EQU 0x19 85 RXF5EID8 EQU 0x1A 86 RXF5EID0 EQU 0x1B 87 88 ; Receive Masks * 89 RXM0SIDH EQU 0x20 90 RXM0SIDL EQU 0x21 91 RXM0EID8 EQU 0x22 92 RXM0EID0 EQU 0x23 93 RXM1SIDH EQU 0x24 94 RXM1SIDL EQU 0x25 95 RXM1EID8 EQU 0x26 96 RXM1EID0 EQU 0x27 97 98 ; Tx Buffer 0 * 99 TXB0CTRL EQU 0x30 100 TXB0SIDH EQU 0x31 101 TXB0SIDL EQU 0x32 102 TXB0EID8 EQU 0x33 103 TXB0EID0 EQU 0x34 104 TXB0DLC EQU 0x35 105 TXB0D0 EQU 0x36 106 TXB0D1 EQU 0x37 107 TXB0D2 EQU 0x38 108 TXB0D3 EQU 0x39 109 TXB0D4 EQU 0x3A 110 TXB0D5 EQU 0x3B 111 TXB0D6 EQU 0x3C 112 TXB0D7 EQU 0x3D 113 114 ; Tx Buffer 1 * 115 TXB1CTRL EQU 0x40 116 TXB1SIDH EQU 0x41 117 TXB1SIDL EQU 0x42 118 TXB1EID8 EQU 0x43 119 TXB1EID0 EQU 0x44 120 TXB1DLC EQU 0x45 121 TXB1D0 EQU 0x46 122 TXB1D1 EQU 0x47 123 TXB1D2 EQU 0x48 124 TXB1D3 EQU 0x49 125 TXB1D4 EQU 0x4A 126 TXB1D5 EQU 0x4B 127 TXB1D6 EQU 0x4C 128 TXB1D7 EQU 0x4D 129 130 ; Tx Buffer 2 * 131 TXB2CTRL EQU 0x50 132 TXB2SIDH EQU 0x51 133 TXB2SIDL EQU 0x52 134 TXB2EID8 EQU 0x53 135 TXB2EID0 EQU 0x54 136 TXB2DLC EQU 0x55 137 TXB2D0 EQU 0x56 138 TXB2D1 EQU 0x57 139 TXB2D2 EQU 0x58 140 TXB2D3 EQU 0x59 141 TXB2D4 EQU 0x5A 142 TXB2D5 EQU 0x5B 143 TXB2D6 EQU 0x5C 144 TXB2D7 EQU 0x5D 145 146 ; Rx Buffer 0 * 147 RXB0CTRL EQU 0x60 148 RXB0SIDH EQU 0x61 149 RXB0SIDL EQU 0x62 150 RXB0EID8 EQU 0x63 151 RXB0EID0 EQU 0x64 152 RXB0DLC EQU 0x65 153 RXB0D0 EQU 0x66 154 RXB0D1 EQU 0x67 155 RXB0D2 EQU 0x68 156 RXB0D3 EQU 0x69 157 RXB0D4 EQU 0x6A 158 RXB0D5 EQU 0x6B 159 RXB0D6 EQU 0x6C 160 RXB0D7 EQU 0x6D 161 162 ; Rx Buffer 1 * 163 RXB1CTRL EQU 0x70 164 RXB1SIDH EQU 0x71 165 RXB1SIDL EQU 0x72 166 RXB1EID8 EQU 0x73 167 RXB1EID0 EQU 0x74 168 RXB1DLC EQU 0x75 169 RXB1D0 EQU 0x76 170 RXB1D1 EQU 0x77 171 RXB1D2 EQU 0x78 172 RXB1D3 EQU 0x79 173 RXB1D4 EQU 0x7A 174 RXB1D5 EQU 0x7B 175 RXB1D6 EQU 0x7C 176 RXB1D7 EQU 0x7D 177 178 179 ; ******************************************************************* 180 ; * Bit register masks * 181 ; ******************************************************************* 182 183 ; TXBnCTRL * 184 TXREQ EQU 0x08 185 TXP EQU 0x03 186 187 ; RXBnCTRL * 188 RXM EQU 0x60 189 BUKT EQU 0x04 190 191 ; CANCTRL * 192 REQOP EQU 0xE0 193 ABAT EQU 0x10 194 CLKEN EQU 0x04 195 CLKPRE EQU 0x03 196 197 ; CANSTAT * 198 ; REQOP EQU 0xE0 199 ICOD EQU 0x0E 200 201 ; CANINTE * 202 RX0IE EQU 0x01 203 RX1IE EQU 0x02 204 TX0IE EQU 0x04 205 TX1IE EQU 0x80 206 TX2IE EQU 0x10 207 ERRIE EQU 0x20 208 WAKIE EQU 0x40 209 IVMIE EQU 0x80 210 211 ; CANINTF * 212 RX0IF EQU 0x01 213 RX1IF EQU 0x02 214 TX0IF EQU 0x04 215 TX1IF EQU 0x80 216 TX2IF EQU 0x10 217 ERRIF EQU 0x20 218 WAKIF EQU 0x40 219 IVMIF EQU 0x80 220 221 ; BFPCTRL * 222 B1BFS EQU 0x20 223 B0BFS EQU 0x10 224 B1BFE EQU 0x08 225 B0BFE EQU 0x04 226 B1BFM EQU 0x02 227 B0BFM EQU 0x01 228 229 ; CNF1 Masks * 230 SJW EQU 0xC0 231 BRP EQU 0x3F 232 233 ; CNF2 Masks * 234 BTLMODE EQU 0x80 235 SAM EQU 0x40 236 PHSEG1 EQU 0x38 237 PRSEG EQU 0x07 238 239 ; CNF3 Masks * 240 WAKFIL EQU 0x40 241 PHSEG2 EQU 0x07 242 243 ; TXRTSCTRL Masks * 244 TXB2RTS EQU 0x04 245 TXB1RTS EQU 0x02 246 TXB0RTS EQU 0x01 247 248 249 ; ******************************************************************* 250 ; * Bit Timing Configuration * 251 ; ******************************************************************* 252 253 ; CNF1 * 254 SJW_1TQ EQU 0x40 255 SJW_2TQ EQU 0x80 256 SJW_3TQ EQU 0x90 257 SJW_4TQ EQU 0xC0 258 259 ; CNF2 * 260 BTLMODE_CNF3 EQU 0x80 261 BTLMODE_PH1_IPT EQU 0x00 262 263 SMPL_3X EQU 0x40 264 SMPL_1X EQU 0x00 265 266 PHSEG1_8TQ EQU 0x38 267 PHSEG1_7TQ EQU 0x30 268 PHSEG1_6TQ EQU 0x28 269 PHSEG1_5TQ EQU 0x20 270 PHSEG1_4TQ EQU 0x18 271 PHSEG1_3TQ EQU 0x10 272 PHSEG1_2TQ EQU 0x08 273 PHSEG1_1TQ EQU 0x00 274 275 PRSEG_8TQ EQU 0x07 276 PRSEG_7TQ EQU 0x06 277 PRSEG_6TQ EQU 0x05 278 PRSEG_5TQ EQU 0x04 279 PRSEG_4TQ EQU 0x03 280 PRSEG_3TQ EQU 0x02 281 PRSEG_2TQ EQU 0x01 282 PRSEG_1TQ EQU 0x00 283 284 ; CNF3 * 285 PHSEG2_8TQ EQU 0x07 286 PHSEG2_7TQ EQU 0x06 287 PHSEG2_6TQ EQU 0x05 288 PHSEG2_5TQ EQU 0x04 289 PHSEG2_4TQ EQU 0x03 290 PHSEG2_3TQ EQU 0x02 291 PHSEG2_2TQ EQU 0x01 292 PHSEG2_1TQ EQU 0x00 293 294 WAKFIL_ENABLED EQU 0x40 295 WAKFIL_DISABLED EQU 0x00 296 297 298 ; ******************************************************************* 299 ; * Control/Configuration Registers * 300 ; ******************************************************************* 301 302 ; CANINTE * 303 RX0IE_ENABLED EQU 0x01 304 RX0IE_DISABLED EQU 0x00 305 RX1IE_ENABLED EQU 0x02 306 RX1IE_DISABLED EQU 0x00 307 G_RXIE_ENABLED EQU 0x03 308 G_RXIE_DISABLED EQU 0x00 309 310 TX0IE_ENABLED EQU 0x04 311 TX0IE_DISABLED EQU 0x00 312 TX1IE_ENABLED EQU 0x08 313 TX2IE_DISABLED EQU 0x00 314 TX2IE_ENABLED EQU 0x10 315 TX2IE_DISABLED EQU 0x00 316 G_TXIE_ENABLED EQU 0x1C 317 G_TXIE_DISABLED EQU 0x00 318 319 ERRIE_ENABLED EQU 0x20 320 ERRIE_DISABLED EQU 0x00 321 WAKIE_ENABLED EQU 0x40 322 WAKIE_DISABLED EQU 0x00 323 IVRE_ENABLED EQU 0x80 324 IVRE_DISABLED EQU 0x00 325 326 ; CANINTF * 327 RX0IF_SET EQU 0x01 328 RX0IF_RESET EQU 0x00 329 RX1IF_SET EQU 0x02 330 RX1IF_RESET EQU 0x00 331 TX0IF_SET EQU 0x04 332 TX0IF_RESET EQU 0x00 333 TX1IF_SET EQU 0x08 334 TX2IF_RESET EQU 0x00 335 TX2IF_SET EQU 0x10 336 TX2IF_RESET EQU 0x00 337 ERRIF_SET EQU 0x20 338 ERRIF_RESET EQU 0x00 339 WAKIF_SET EQU 0x40 340 WAKIF_RESET EQU 0x00 341 IVRF_SET EQU 0x80 342 IVRF_RESET EQU 0x00 343 344 ; CANCTRL * 345 REQOP_CONFIG EQU 0x80 346 REQOP_LISTEN EQU 0x60 347 REQOP_LOOPBACK EQU 0x40 348 REQOP_SLEEP EQU 0x20 349 REQOP_NORMAL EQU 0x00 350 351 ABORT EQU 0x10 352 353 CLKOUT_ENABLED EQU 0x04 354 CLKOUT_DISABLED EQU 0x00 355 CLKOUT_PRE_8 EQU 0x03 356 CLKOUT_PRE_4 EQU 0x02 357 CLKOUT_PRE_2 EQU 0x01 358 CLKOUT_PRE_1 EQU 0x00 359 360 ; CANSTAT * 361 OPMODE_CONFIG EQU 0x80 362 OPMODE_LISTEN EQU 0x60 363 OPMODE_LOOPBACK EQU 0x40 364 OPMODE_SLEEP EQU 0x20 365 OPMODE_NORMAL EQU 0x00 366 367 368 ; RXBnCTRL * 369 RXM_RCV_ALL EQU 0x60 370 RXM_VALID_EXT EQU 0x40 371 RXM_VALID_STD EQU 0x20 372 RXM_VALID_ALL EQU 0x00 373 374 RXRTR_REMOTE EQU 0x08 375 RXRTR_NO_REMOTE EQU 0x00 376 377 BUKT_ROLLOVER EQU 0x04 378 BUKT_NO_ROLLOVER EQU 0x00 379 380 FILHIT0_FLTR_1 EQU 0x01 381 FILHIT0_FLTR_0 EQU 0x00 382 383 FILHIT1_FLTR_5 EQU 0x05 384 FILHIT1_FLTR_4 EQU 0x04 385 FILHIT1_FLTR_3 EQU 0x03 386 FILHIT1_FLTR_2 EQU 0x02 387 FILHIT1_FLTR_1 EQU 0x01 388 FILHIT1_FLTR_0 EQU 0x00 389 390 391 ; TXBnCTRL * 392 TXREQ_SEND EQU 0x08 393 TXREQ_ABORT EQU 0x00 394 395 TXP_HIGHEST EQU 0x03 396 TXP_INTER_HIGH EQU 0x02 397 TXP_INTER_LOW EQU 0x01 398 TXP_LOWEST EQU 0x00 399 400 401 ; ******************************************************************* 402 ; * Register Bit Masks * 403 ; ******************************************************************* 404 405 DLC_0 EQU 0x00 406 DLC_1 EQU 0x01 407 DLC_2 EQU 0x02 408 DLC_3 EQU 0x03 409 DLC_4 EQU 0x04 410 DLC_5 EQU 0x05 411 DLC_6 EQU 0x06 412 DLC_7 EQU 0x07 413 DLC_8 EQU 0x08 414 415 416 ; ******************************************************************* 417 ; * CAN SPI commands * 418 ; ******************************************************************* 419 420 CAN_RESET EQU 0xC0 421 CAN_READ EQU 0x03 422 CAN_WRITE EQU 0x02 423 CAN_RTS EQU 0x80 424 CAN_RTS_TXB0 EQU 0x81 425 CAN_RTS_TXB1 EQU 0x82 426 CAN_RTS_TXB2 EQU 0x83 427 CAN_RD_STATUS EQU 0xA0 428 CAN_BIT_MODIFY EQU 0x05 429 430 431 ; ******************************************************************* 432 ; * Miscellaneous * 433 ; ******************************************************************* 434 435 DUMMY_BYTE EQU 0x00 436 TXB0 EQU 0x31 437 TXB1 EQU 0x41 438 TXB2 EQU 0x51 439 RXB0 EQU 0x61 440 RXB1 EQU 0x71 441 EXIDE_SET EQU 0x08 442 EXIDE_RESET EQU 0x00 442 31 include "tests/p12c672.inc" 32 33 34 35 PCL EQU 2 36 STATUS EQU 3 37 GPIO EQU 5 38 39 40 RP0 EQU 5 41 RP1 EQU 6 42 43 INTCON EQU 0xb 44 GPIF EQU 0 45 INTF EQU 1 46 T0IF EQU 2 47 GPIE EQU 3 48 INTE EQU 4 49 T0IE EQU 5 50 GIE EQU 7 51 52 53 PCLATH EQU 10 54 TRISIO EQU 0x85 55 56 TMR0 EQU 1 57 58 OPTION_REG EQU 0x81 59 60 ADRES EQU 0x1E 61 62 ADCON0 EQU 0x1F 63 ADCON1 EQU 0x9f 64 65 GO EQU 6 66 67 68 GO_DONE EQU 2 69 CHS0 EQU 3 70 CHS1 EQU 4 71 72 Z EQU 2 73 DC EQU 1 74 C EQU 0 75 75 33 ; *********************************************** 34 ; * Setup the PIC12C672 configuration Word * 35 ; *********************************************** 36 37 __CONFIG _CP_OFF & _WDT_OFF & _MCLRE_OFF & _INTRC_OSC 38 39 40 ; *********************************************** 41 ; * Constants definitions * 42 ; *********************************************** 43 TMR_COUNT EQU 0xD9 ; Timer Reload value: 44 ; 0xD9 = 38 * 256 * 1us = 9.728ms 45 46 ; *********************************************** 47 ; * Variable definitions * 48 ; *********************************************** 49 temp EQU 0x20 50 temp1 EQU 0x21 51 byte_cnt EQU 0x22 52 addr EQU 0x23 53 tmp_data EQU 0x24 54 55 ; *********************************************** 56 ; * PIC Initialization * 57 ; *********************************************** 58 59 org 0x00 60 000000 2805 goto start ; Jump around ISR vector 61 62 ; *********************************************** 63 ; * Interrupt service vector initialization * 64 ; *********************************************** 65 org 0x04 66 000004 2848 goto isr ; Point ISR vector to the ISR handler 67 68 ; *********************************************** 69 ; * Start of Main Code * 70 ; *********************************************** 71 start 72 000005 1683 bsf STATUS,RP0 ; select bank1 73 000006 3087 movlw 0x87 ; Disable internal pullups 74 ; Interrupt on negative going edge on GP2 75 ; Prescaler = 1:256 76 77 000007 0081 movwf OPTION_REG ; Load the OPTION register 78 79 000008 300B movlw 0x0B ; --001011 80 000009 0085 movwf TRISIO ; set all ports output except GP3/1/0 81 82 00000A 158B bsf INTCON,GPIE ; enable GPIO Interrupt on change 83 84 00000B 3004 movlw 0x04 ; GP4&2 = DIO, GP0&1= ADC, Vref=VDD 85 00000C 009F movwf ADCON1 ; 86 87 00000D 3004 movlw 0x04 ; GPIE set - interrupt on pin change 88 ; GIE cleared - global interrupts disabled 89 00000E 1283 bcf STATUS,RP0 ; select bank0 90 91 92 93 ; Initialize the A/D converter 94 95 00000F 3040 movlw 0x40 ; AN0 conversion clock = Fosc/8 (TAD=2us) 96 000010 009F movwf ADCON0 ; Turn off A/D module 97 98 ; Initialize Timer0 99 100 000011 30D9 movlw TMR_COUNT ; Initialize Timer0 101 000012 0081 movwf TMR0 ; Timer0 interrupt every 9.728mS 102 103 ; Set up initial conditions for the SPI 104 105 000013 3024 movlw 0x24 ; CS high, INT high, data/clk low 106 000014 0085 movwf GPIO ; write to port 107 108 000015 1685 bsf GPIO,cs_pin ; set CS pin high 109 000016 1105 bcf GPIO,sck_pin ; clear the sck pin 110 000017 1205 bcf GPIO,sdo_pin ; clear the sdo pin 111 112 000018 201D call mcp2510_init ; initialize the mcp2510 113 114 ; ******************************************* 115 ; * Main wait loop * 116 ; ******************************************* 117 118 wait ; wait for interrupt to occur 119 000019 0063 sleep ; sleep while not processing a message 120 00001A 0000 nop ; NOP executed when waking up from sleep 121 00001B 0000 nop ; NOP executed after ISR completes 122 00001C 2819 goto wait ; go back to sleep and wait 123 124 125 ; *********************************************** 126 ; * MCP2510 Initialization * 127 ; *********************************************** 128 129 mcp2510_init 130 00001D 3002 movlw CAN_WRITE ; write command 131 00001E 1285 bcf GPIO,cs_pin ; lower CS to enable MCP2510 132 00001F 210B call spi_send ; send comand 133 000020 300F movlw CANCTRL ; select CANCTRL register address 134 000021 210B call spi_send ; and send it 135 000022 3080 movlw REQOP_CONFIG ; Request Config Mode 136 000023 210B call spi_send ; send data 137 000024 1685 bsf GPIO,cs_pin ; raise CS to terminate operation 138 000025 1105 bcf GPIO,sck_pin ; set clock and 139 000026 1205 bcf GPIO,sdo_pin ; data pins low 140 141 000027 3071 movlw 0x71 ; number of addresses to be written 142 000028 00A2 movwf byte_cnt ; load into byte counter 143 000029 3002 movlw CAN_WRITE ; write command 144 00002A 1285 bcf GPIO,cs_pin ; enable MCP2510 145 00002B 210B call spi_send ; send command 146 00002C 3000 movlw 0x00 ; start writting at address 0x00 147 00002D 210B call spi_send ; send address 148 00002E 3001 movlw 0x01 149 00002F 00A3 movwf addr 150 seq_wr ; sequential write loop 151 000030 3007 movlw HIGH reg_init_tbl ; get high byte of reg_int_tbl address 152 000031 008A movwf PCLATH ; load into high byte of PC counter 153 000032 0823 movfw addr ; write into jump table pointer (addr) 154 000033 03A3 decf addr, 1 ; 155 ;; movf addr, W 156 000034 0823 movfw addr 157 000035 2700 call reg_init_tbl ; fetch byte to be written 158 000036 210B call spi_send ; send it to MCP2510 159 000037 0AA3 incf addr,1 ; increment the jump table pointer 160 000038 0AA3 incf addr,1 ; twice to point to the next byte 161 000039 0BA2 decfsz byte_cnt,1 ; decrement the byte counter and test for zero 162 00003A 2830 goto seq_wr ; not done so repeat 163 00003B 1685 bsf GPIO,cs_pin ; raise CS to terminate operation 164 165 00003C 3002 movlw CAN_WRITE ; write command 166 00003D 1285 bcf GPIO,cs_pin ; enable MCP2510 167 00003E 210B call spi_send 168 00003F 300F movlw CANCTRL ; write to CANCTRL register 169 000040 210B call spi_send 170 000041 3000 movlw REQOP_NORMAL ; Normal Mode 171 000042 210B call spi_send 172 000043 1685 bsf GPIO,cs_pin ; terminate operation 173 174 000044 3000 movlw 0x00 ; clear byte_cnt variable 175 000045 00A2 movwf byte_cnt 176 177 000046 178B bsf INTCON,GIE ; Enable Interrupts 178 000047 0008 return 179 180 181 182 ; ******************************************************************* 183 ; * Interrupt Service Routine * 184 ; * The ISR determines whether a TMR0 interrupt or an external INT * 185 ; * pin interrupt occurs and then proceeds accordingly * 186 ; ******************************************************************* 187 isr 188 000048 1303 bcf STATUS,RP1 ; select bank 0/1 189 190 000049 1E8B btfss INTCON,T0IE ; Timer0 interrupt? 191 00004A 285D goto intpin ; No, so jump to external interrupt pin ISR 192 193 00004B 30D9 movlw TMR_COUNT ; reload 194 00004C 0081 movwf TMR0 ; Timer0 195 196 00004D 119F bcf ADCON0,CHS0 ; select ADC channel 0 197 00004E 20FF call adc_cnv ; go do the conversion 198 199 00004F 1285 bcf GPIO,cs_pin ; enable MCP2510 200 201 000050 3002 movlw CAN_WRITE ; send write command to MCP2510 202 000051 210B call spi_send ; 203 204 000052 3036 movlw TXB0D0 ; set write address to TXB0D0 205 000053 210B call spi_send ; 206 207 000054 081E movfw ADRES ; write ADC conversion result 208 000055 210B call spi_send ; 209 000056 1685 bsf GPIO,cs_pin ; terminate SPI operation 210 211 212 000057 1285 bcf GPIO,cs_pin ; enable MCP2510 213 000058 3081 movlw CAN_RTS_TXB0 ; Send RTS command for TXB0 214 000059 210B call spi_send 215 00005A 1685 bsf GPIO,cs_pin ; terminate operation 216 217 00005B 110B bcf INTCON, T0IF ; clear TMR0 interrupt flag 218 00005C 0008 return ; exit isr 219 220 intpin ; Message received interrupt 221 222 00005D 3003 movlw CAN_READ 223 00005E 1285 bcf GPIO,cs_pin ; lower CS line 224 00005F 210B call spi_send ; send read command to MCP2510 225 226 ; Check for RXB1IF flag by reading 227 000060 302C movlw CANINTF ; the interrupt flag register (CANINTF) 228 000061 210B call spi_send 229 000062 211E call spi_rx ; read the data from the MCP2510 230 000063 1685 bsf GPIO,cs_pin ; terminate SPI read 231 232 000064 00A4 movwf tmp_data ; save CANINTF value 233 234 000065 18A4 btfsc tmp_data,1 ; test CANINTF for RX1IF 235 000066 2089 call msg_rcvd ; if RX1IF set go process message 236 237 000067 1EA4 btfss tmp_data,5 ; test CANINTF for ERRIF 238 000068 206F call can_err ; if ERRIF set go process CAN error 239 240 000069 30DD movlw B'11011101' ; mask off RXB1IF and ERRIF bits 241 00006A 05A4 andwf tmp_data,1 ; of CANINTF 242 00006B 1903 btfsc STATUS,Z ; if any bit set process invalid interrupt 243 244 00006C 2084 call sys_err ; Not an error interrupt so initiate an invalid interrupt 245 ; occured message. 246 247 00006D 100B bcf INTCON,GPIF ; reset interrupt flag 248 00006E 0009 retfie ; return to main routine 249 250 251 ; ******************************************************************* 252 ; * CAN Error routine * 253 ; * This routine reads the value of the MCP2510 Error flag (EFLG) * 254 ; * register, writes it to byte 0 of TXB1, and then transmits the * 255 ; * TXB1 message * 256 ; ******************************************************************* 257 can_err 258 259 00006F 3003 movlw CAN_READ ; SPI Read operation 260 000070 1285 bcf GPIO,cs_pin ; enable MCP2510 261 000071 210B call spi_send ; 262 000072 302D movlw EFLG ; EFLG register to be read 263 000073 210B call spi_send ; 264 000074 211E call spi_rx ; read the data 265 000075 1685 bsf GPIO,cs_pin ; terminate SPI operation 266 000076 00A4 movwf tmp_data ; save the value of EFLG register 267 268 000077 3002 movlw CAN_WRITE ; now write to MCP2510 269 000078 1285 bcf GPIO,cs_pin ; 270 000079 210B call spi_send ; 271 00007A 3046 movlw TXB1D0 ; write to data byte 0 of TXB1 272 00007B 210B call spi_send ; 273 00007C 0824 movfw tmp_data ; write EFLG register contents 274 00007D 210B call spi_send ; 275 00007E 1685 bsf GPIO,cs_pin ; terminate SPI operation 276 277 00007F 3082 movlw CAN_RTS_TXB1 ; send request to send 278 000080 1285 bcf GPIO,cs_pin ; for transmit buffer 1 279 000081 210B call spi_send 280 000082 1685 bsf GPIO,cs_pin 281 ; exit isr and re-enable interrupts 282 000083 0009 retfie 283 284 285 ; ******************************************************************* 286 ; * System Error Handler Routine * 287 ; * This routines transmits the TXB2 message to indicate that a * 288 ; * unidintifiable system error has occured. * 289 ; ******************************************************************* 290 sys_err 291 000084 3083 movlw CAN_RTS_TXB2 ; send request to send 292 000085 1285 bcf GPIO,cs_pin ; for transmit buffer 2 293 000086 210B call spi_send ; when a system error occurs 294 000087 1685 bsf GPIO,cs_pin 295 296 000088 0009 retfie 297 298 299 ; ******************************************************************* 300 ; * CAN Msg Received Routine * 301 ; * This routine is called when a message has been received into * 302 ; * TXB0 of the MCP2510. This routine reads the filter bits to * 303 ; * determine the type of message received and then initiates the * 304 ; * appropriate response. * 305 ; ******************************************************************* 306 msg_rcvd 307 000089 3003 movlw CAN_READ ; SPI read command 308 00008A 1285 bcf GPIO,cs_pin ; enable MCP2510 309 00008B 210B call spi_send 310 311 00008C 3060 movlw RXB0CTRL ; Read buffer 0 control register 312 00008D 210B call spi_send 313 00008E 211E call spi_rx 314 00008F 1685 bsf GPIO,cs_pin ; terminate function 315 316 000090 3907 andlw B'00000111' ; mask off all but the FILHIT bits 317 000091 00A0 movwf temp ; store value in temp 318 319 000092 3001 movlw 0x01 ; 320 000093 02A0 subwf temp,1 321 000094 1903 btfsc STATUS,Z ; filter 1 match? 322 000095 28A2 goto filter1 323 324 000096 3002 movlw 0x02 325 000097 02A0 subwf temp,1 326 000098 1903 btfsc STATUS,Z ; filter 2 match 327 000099 28AE goto filter2 328 329 00009A 3003 movlw 0x03 330 00009B 02A0 subwf temp,1 331 00009C 1903 btfsc STATUS,Z ; filter 3 match 332 00009D 28BD goto filter3 333 334 00009E 3004 movlw 0x04 335 00009F 02A0 subwf temp,1 336 0000A0 1903 btfsc STATUS,Z ; filter 4 match 337 0000A1 28D3 goto filter4 338 339 filter1 340 0000A2 20ED call wrt_txb0sidh ; load the transmit buffer SIDH register 341 342 0000A3 159F bsf ADCON0,CHS0 ; select ADC channel 1 343 0000A4 20FF call adc_cnv ; go do the conversion 344 345 0000A5 1285 bcf GPIO,cs_pin ; enable MCP2510 346 0000A6 3002 movlw CAN_WRITE ; send write command to MCP2510 347 0000A7 210B call spi_send ; 348 0000A8 3036 movlw TXB0D0 ; set write address to TXB0D0 349 0000A9 210B call spi_send ; 350 0000AA 081E movfw ADRES ; write ADC conversion result 351 0000AB 210B call spi_send ; 352 0000AC 1685 bsf GPIO,cs_pin ; terminate SPI operation 353 354 0000AD 28E8 goto filter_done 355 356 filter2 357 0000AE 20ED call wrt_txb0sidh ; load the transmit buffer SIDH register 358 359 0000AF 1285 bcf GPIO,cs_pin ; enable MCP2510 360 0000B0 3003 movlw CAN_READ ; send read command to MCP2510 361 0000B1 210B call spi_send ; 362 0000B2 300D movlw TXRTSCTRL ; set read address to TXRTSCTRL 363 0000B3 210B call spi_send ; 364 0000B4 211E call spi_rx ; read data 365 0000B5 1685 bsf GPIO,cs_pin 366 367 0000B6 1285 bcf GPIO,cs_pin 368 0000B7 3002 movlw CAN_WRITE ; write TXTRTSCTRL value 369 0000B8 210B call spi_send ; to data byte zero of 370 0000B9 3036 movlw TXB0D0 ; transmit buffer zero 371 0000BA 210B call spi_send ; 372 0000BB 1685 bsf GPIO,cs_pin ; terminate SPI operation 373 374 0000BC 28E8 goto filter_done 375 376 filter3 377 0000BD 20ED call wrt_txb0sidh ; load the transmit buffer SIDH register 378 379 0000BE 3003 movlw CAN_READ ; Read contents of receive buffer zero 380 0000BF 1285 bcf GPIO,cs_pin ; byte zero to get value to write to 381 0000C0 210B call spi_send ; GP output pin of MCP2510 382 0000C1 3076 movlw RXB1D0 ; 383 0000C2 210B call spi_send 384 0000C3 211E call spi_rx 385 0000C4 1685 bsf GPIO,cs_pin 386 0000C5 00A4 movwf tmp_data ; store value in tmp_data 387 388 0000C6 3005 movlw CAN_BIT_MODIFY ; use bit modify command to 389 0000C7 1285 bcf GPIO,cs_pin ; set/reset the B0BFS bit of BFPCTRL register 390 0000C8 210B call spi_send 391 0000C9 300C movlw BFPCTRL 392 0000CA 210B call spi_send 393 0000CB 3010 movlw B0BFS 394 0000CC 210B call spi_send 395 396 0000CD 30FF movlw 0xFF ; assume that B0BFS is to be set 397 0000CE 1C24 btfss tmp_data,0 ; test the value received in message and if it is 0 398 0000CF 3000 movlw 0x00 ; load w register to reset bit in BFPCTRL register 399 400 0000D0 210B call spi_send 401 0000D1 1685 bsf GPIO,cs_pin 402 403 0000D2 28E8 goto filter_done 404 405 filter4 406 0000D3 20ED call wrt_txb0sidh ; load the transmit buffer SIDH register 407 408 0000D4 3003 movlw CAN_READ ; Read contents of receive buffer zero 409 0000D5 1285 bcf GPIO,cs_pin ; byte zero to get value to write to 410 0000D6 210B call spi_send ; GP output pin of MCP2510 411 0000D7 3076 movlw RXB1D0 ; 412 0000D8 210B call spi_send 413 0000D9 211E call spi_rx 414 0000DA 1685 bsf GPIO,cs_pin 415 0000DB 00A4 movwf tmp_data ; store value in tmp_data 416 417 0000DC 3005 movlw CAN_BIT_MODIFY ; use bit modify command to 418 0000DD 1285 bcf GPIO,cs_pin ; set/reset the B0BFS bit of BFPCTRL register 419 0000DE 210B call spi_send 420 0000DF 300C movlw BFPCTRL 421 0000E0 210B call spi_send 422 0000E1 3020 movlw B1BFS 423 0000E2 210B call spi_send 424 425 0000E3 30FF movlw 0xFF ; assume that B1BFS is to be set 426 0000E4 1C24 btfss tmp_data,0 ; test the value received in message and if it is 0 427 0000E5 3000 movlw 0x00 ; load w register to reset bit in BFPCTRL register 428 429 0000E6 210B call spi_send 430 0000E7 1685 bsf GPIO,cs_pin 431 432 filter_done 433 0000E8 3081 movlw CAN_RTS_TXB0 ; last step is to send the 434 0000E9 1285 bcf GPIO,cs_pin ; request to send command for 435 0000EA 210B call spi_send ; transmit buffer zero 436 0000EB 1685 bsf GPIO,cs_pin 437 438 0000EC 0008 return 439 440 ; ******************************************************************* 441 ; * write TXB0SIDH * 442 ; * This routine reads the SIDH register from the received message * 443 ; * and then sets the SID3 bit and writes the new value to the TX * 444 ; * buffer. * 445 ; ******************************************************************* 446 wrt_txb0sidh 447 0000ED 3003 movlw CAN_READ ; SPI read command 448 0000EE 1285 bcf GPIO,cs_pin ; enable MCP2510 449 0000EF 210B call spi_send 450 0000F0 3061 movlw RXB0SIDH ; Read received SIDH register 451 0000F1 210B call spi_send 452 0000F2 211E call spi_rx 453 0000F3 1685 bsf GPIO,cs_pin ; terminate function 454 455 0000F4 00A4 movwf tmp_data ; store SIDH value in data 456 457 0000F5 1285 bcf GPIO,cs_pin 458 0000F6 3002 movlw CAN_WRITE 459 0000F7 210B call spi_send 460 0000F8 3031 movlw TXB0SIDH ; write to the SIDH register 461 0000F9 210B call spi_send ; 462 0000FA 0824 movfw tmp_data ; retreive SIDH value of received message 463 ; bsf W,0 ; set bit SID3 high 464 0000FB 3801 iorlw 1 465 0000FC 210B call spi_send ; 466 0000FD 1685 bsf GPIO,cs_pin 467 0000FE 0008 return 468 469 470 471 ; ******************************************************************* 472 ; * Anadlog to Digital Conversion Routine * 473 ; * This routine initiates the A/D conversion. The ADC channel * 474 ; * select bits (CHS1:0) have to be set prior to this routine being * 475 ; * called. The routine waits for the conversion to complete * 476 ; * before returning to the calling function. * 477 ; ******************************************************************* 478 adc_cnv 479 0000FF 171F bsf ADCON0,GO 480 adc_busy 481 000100 191F btfsc ADCON0,GO_DONE ; wait for ADC to complete 482 000101 2900 goto adc_busy 483 484 000102 3002 movlw CAN_WRITE ; SPI write command 485 000103 1285 bcf GPIO,cs_pin ; lower CS line 486 000104 210B call spi_send ; send write command to MCP2510 487 000105 3036 movlw TXB0D0 ; data being written to data byte zero of buff 0 488 000106 210B call spi_send ; 489 000107 081E movf ADRES,0 ; Move ADC value to W register 490 000108 210B call spi_send ; send to MCP2510 491 000109 1685 bsf GPIO,cs_pin ; terminate SPI command 492 00010A 0008 return 493 494 495 ; ************************************************** 496 ; * Include the custom three wire SPI support file * 497 ; ************************************************** 498 499 include "tests/spi.inc" ; SPI routines 500 ; *********************************************** 501 ; * spi.asm * 502 ; * Revision 1.0 May 2000 * 503 ; * Developed by Rick Stoneking * 504 ; * Developed using MPLAB V4.12 and MPASM V2.3 * 505 ; * * 506 ; * This code implements SPI communications for * 507 ; * the Microchip PIC12C672 8 pin micro * 508 ; * using a three wire interface * 509 ; * * 510 ; *********************************************** 511 512 ; *********************************************** 513 ; * Define I/O pin assignments * 514 ; *********************************************** 515 cs_pin EQU 5 516 sdi_pin EQU 4 517 sdo_pin EQU 4 518 int_pin EQU 3 519 sck_pin EQU 2 520 521 ; *********************************************** 522 ; * Variable definitions * 523 ; *********************************************** 524 525 526 ; *********************************************** 527 ; * SPI_SEND * 528 ; * This routine sends a single byte out. The * 529 ; * byte to be transmitted must be loaded into * 530 ; * the w register prior to calling this * 531 ; * routine. * 532 ; * The routine is designed to allow * 533 ; * sending multiple bytes by using consecutive * 534 ; * calls, therefore it is necessary for the * 535 ; * calling routine to handle the CS line * 536 ; * before calling the routine for the first * 537 ; * time, and after sending the last byte. * 538 ; *********************************************** 539 spi_send ; w reg must have data byte to be sent in it 540 00010B 00A0 movwf temp ; save data byte 541 00010C 1683 bsf STATUS,RP0 ; select bank1 542 00010D 3008 movlw 0x08 ; set GP4 to output 543 00010E 0085 movwf TRISIO 544 00010F 1283 bcf STATUS,RP0 ; select bank0 545 000110 3008 movlw 8 546 000111 00A1 movwf temp1 ; bit counter 547 548 write_loop 549 000112 0DA0 rlf temp,1 ; move bit into carry flag 550 000113 1105 bcf GPIO,sck_pin ; set sck low 551 000114 1803 btfsc STATUS,C ; test and if clear skip next instruction 552 000115 2918 goto send_hi 553 000116 1205 bcf GPIO,sdo_pin 554 000117 2919 goto wr_clock 555 send_hi 556 000118 1605 bsf GPIO,sdo_pin 557 wr_clock 558 000119 1505 bsf GPIO,sck_pin ; set sck high 559 00011A 0BA1 decfsz temp1,1 560 00011B 2912 goto write_loop 561 00011C 1205 bcf GPIO,sdo_pin ; exit routine with SDO low 562 00011D 3400 retlw 0 563 564 ; *********************************************** 565 ; * SPI_RX * 566 ; * This routine receives a single byte. The * 567 ; * received byte is in the w register upon * 568 ; * returning to the calling function. * 569 ; * The routine is designed to allow receiving * 570 ; * multiple bytes by using consecutive * 571 ; * calls, therefore it is necessary for the * 572 ; * calling routine to handle the CS line * 573 ; * before calling the routine for the first * 574 ; * time, and after receiving the last byte. * 575 ; *********************************************** 576 spi_rx 577 00011E 1683 bsf STATUS,RP0 ; select bank1 578 00011F 3018 movlw 0x18 ; set GP4 to input 579 000120 0085 movwf TRISIO 580 000121 1283 bcf STATUS,RP0 ; select bank0 581 000122 3000 movlw 0 582 000123 00A0 movwf temp 583 000124 3008 movlw 8 ; set bit count 584 000125 00A1 movwf temp1 585 rd_loop 586 000126 1105 bcf GPIO,sck_pin 587 000127 0DA0 rlf temp,1 ; rotate is done here so that we do 588 ; not rotate after bit counter = 0 589 000128 1A05 btfsc GPIO,sdi_pin ; check input pin 590 000129 292C goto bit_high ; 591 00012A 1020 bcf temp,0 592 00012B 292D goto shift 593 bit_high 594 00012C 1420 bsf temp,0 595 shift 596 00012D 1505 bsf GPIO,sck_pin ; raise clock 597 00012E 0BA1 decfsz temp1,1 598 00012F 2926 goto rd_loop 599 000130 3420 retlw temp 600 601 602 602 501 502 ; ******************************************************************* 503 ; * MCP2510 register initialization table * 504 ; * Store at the end of ROM memory * 505 ; * Note that all addresses are initialized to simplify the * 506 ; * initialization code. * 507 ; ******************************************************************* 508 509 org 0x0700 ; Initialization table address 510 reg_init_tbl 511 000700 0782 addwf PCL, 1 ; Register Addr 512 ; --------- ---- 513 000701 34FF retlw 0xff ; RXF0SIDH 0x00 514 000702 34FF retlw 0xff ; RXF0SIDL 0x01 515 000703 34FF retlw 0xff ; RXF0EID8 0x02 516 000704 34FF retlw 0xff ; RXF0EID0 0x03 517 000705 34FF retlw 0xff ; RXF1SIDH 0x04 518 000706 34FF retlw 0xff ; RXF1SIDL 0x05 519 000707 34FF retlw 0xff ; RXF1EID8 0x06 520 000708 34FF retlw 0xff ; RXF1EID0 0x07 521 000709 347E retlw 0x7e ; RXF2SIDH 0x08 Filter 2 matches 0x3f0 522 00070A 3400 retlw 0x00 ; RXF2SIDL 0x09 523 00070B 34FF retlw 0xff ; RXF2EID8 0x0A 524 00070C 34FF retlw 0xff ; RXF2EID0 0x0B 525 00070D 343C retlw 0x3c ; BFPCTRL 0x0C BFP pins as digital outputs, initial state hi 526 00070E 3400 retlw 0x00 ; TXRTSCTRL 0x0D TXRTS pins as digital inputs 527 00070F 3480 retlw 0x80 ; CANSTAT 0x0E 528 000710 3480 retlw 0x80 ; CANCTRL 0x0F 529 530 000711 347E retlw 0x7e ; RXF3SIDH 0x10 Filter 3 matches 0x3f1 531 000712 3420 retlw 0x20 ; RXF3SIDL 0x11 532 000713 34FF retlw 0xff ; RXF3EID8 0x12 533 000714 34FF retlw 0xff ; RXF3EID0 0x13 534 000715 347E retlw 0x7e ; RXF4SIDH 0x14 Filter 4 matches 0x3f2 535 000716 3440 retlw 0x40 ; RXF4SIDL 0x15 536 000717 34FF retlw 0xff ; RXF4EID8 0x16 537 000718 34FF retlw 0xff ; RXF4EID0 0x17 538 000719 347E retlw 0x7e ; RXF5SIDH 0x18 Filter 5 matches 0x3f3 539 00071A 3450 retlw 0x50 ; RXF5SIDL 0x19 540 00071B 34FF retlw 0xff ; RXF5EID8 0x1A 541 00071C 34FF retlw 0xff ; RXF5EID0 0x1B 542 00071D 3400 retlw 0x00 ; TEC 0x1C 543 00071E 3400 retlw 0x00 ; REC 0x1D 544 00071F 3480 retlw 0x80 ; CANSTAT 0x1E 545 000720 3480 retlw 0x80 ; CANCTRL 0x1F 546 547 000721 34FF retlw 0xff ; RXM0SIDH 0x20 Enable all mask bits so that no msg's 548 000722 34FF retlw 0xff ; RXM0SIDL 0x21 are received into RXB0 549 000723 34FF retlw 0xff ; RXM0EID8 0x22 550 000724 34FF retlw 0xff ; RXM0EID0 0x23 551 000725 347E retlw 0x7e ; RXM1SIDH 0x24 Set RXM1 to match msg ID's of 0x3f0 to 0x3ff 552 000726 3400 retlw 0x00 ; RXM1SIDL 0x25 553 000727 3400 retlw 0x00 ; RXM1EID8 0x26 554 000728 3400 retlw 0x00 ; RXM1EID0 0x27 555 000729 3402 retlw 0x02 ; CNF3 0x28 PHSEG2 = 3TQ 556 00072A 3490 retlw 0x90 ; CNF2 0x29 PHSEG1 = 3TQ, PRSEG = 1TQ 557 00072B 3403 retlw 0x03 ; CNF1 0x2A SJW = 1TQ, BRP set to 4 558 00072C 3422 retlw 0x22 ; CANINTE 0x2B MERRIE and RX1IE enabled 559 00072D 3400 retlw 0x00 ; CANINTF 0x2C 560 00072E 3400 retlw 0x00 ; EFLG 0x2D 561 00072F 3480 retlw 0x80 ; CANSTAT 0x2E 562 000730 3480 retlw 0x80 ; CANCTRL 0x2F 563 564 000731 3403 retlw 0x03 ; TXB0CTRL 0x30 Highest priority 565 000732 347E retlw 0x7e ; TXB0SIDH 0x31 566 000733 3400 retlw 0x00 ; TXB0SIDL 0x32 567 000734 3400 retlw 0x00 ; TXB0EID8 0x33 568 000735 3400 retlw 0x00 ; TXB0EID0 0x34 569 000736 3401 retlw 0x01 ; TXB0DLC 0x35 570 000737 3400 retlw 0x00 ; TXB0DB0 0x36 571 000738 3400 retlw 0x00 ; TXB0DB1 0x37 572 000739 3400 retlw 0x00 ; TXB0DB2 0x38 573 00073A 3400 retlw 0x00 ; TXB0DB3 0x39 574 00073B 3400 retlw 0x00 ; TXB0DB4 0x3A 575 00073C 3400 retlw 0x00 ; TXB0DB5 0x3B 576 00073D 3400 retlw 0x00 ; TXB0DB6 0x3C 577 00073E 3400 retlw 0x00 ; TXB0DB7 0x3D 578 00073F 3480 retlw 0x80 ; CANSTAT 0x3E 579 000740 3480 retlw 0x80 ; CANCTRL 0x3F 580 581 000741 3403 retlw 0x03 ; TXB1CTRL 0x40 Highest priority 582 000742 347E retlw 0x7e ; TXB1SIDH 0x41 583 000743 34E0 retlw 0xe0 ; TXB1SIDL 0x42 584 000744 3400 retlw 0x00 ; TXB1EID8 0x43 585 000745 3400 retlw 0x00 ; TXB1EID0 0x44 586 000746 3401 retlw 0x01 ; TXB1DLC 0x45 587 000747 3400 retlw 0x00 ; TXB1DB0 0x46 588 000748 3400 retlw 0x00 ; TXB1DB1 0x47 589 000749 3400 retlw 0x00 ; TXB1DB2 0x48 590 00074A 3400 retlw 0x00 ; TXB1DB3 0x49 591 00074B 3400 retlw 0x00 ; TXB1DB4 0x4A 592 00074C 3400 retlw 0x00 ; TXB1DB5 0x4B 593 00074D 3400 retlw 0x00 ; TXB1DB6 0x4C 594 00074E 3400 retlw 0x00 ; TXB1DB7 0x4D 595 00074F 3480 retlw 0x80 ; CANSTAT 0x4E 596 000750 3480 retlw 0x80 ; CANCTRL 0x4F 597 598 000751 3403 retlw 0x03 ; TXB2CTRL 0x50 599 000752 347E retlw 0x7e ; TXB2SIDH 0x51 600 000753 34E0 retlw 0xe0 ; TXB2SIDL 0x52 601 000754 3400 retlw 0x00 ; TXB2EID8 0x53 602 000755 3400 retlw 0x00 ; TXB2EID0 0x54 603 000756 3400 retlw 0x00 ; TXB2DLC 0x55 604 000757 3400 retlw 0x00 ; TXB2DB0 0x56 605 000758 3400 retlw 0x00 ; TXB2DB1 0x57 606 000759 3400 retlw 0x00 ; TXB2DB2 0x58 607 00075A 3400 retlw 0x00 ; TXB2DB3 0x59 608 00075B 3400 retlw 0x00 ; TXB2DB4 0x5A 609 00075C 3400 retlw 0x00 ; TXB2DB5 0x5B 610 00075D 3400 retlw 0x00 ; TXB2DB6 0x5C 611 00075E 3400 retlw 0x00 ; TXB2DB7 0x5D 612 00075F 3480 retlw 0x80 ; CANSTAT 0x5E 613 000760 3480 retlw 0x80 ; CANCTRL 0x5F 614 615 000761 3420 retlw 0x20 ; RXB0CTRL 0x60 Receive only Standard Id's that match Masks/Filters 616 000762 3400 retlw 0x00 ; RXB0SIDH 0x61 617 000763 3400 retlw 0x00 ; RXB0SIDL 0x62 618 000764 3400 retlw 0x00 ; RXB0EID8 0x63 619 000765 3400 retlw 0x00 ; RXB0EID0 0x64 620 000766 3400 retlw 0x00 ; RXB0DLC 0x65 621 000767 3400 retlw 0x00 ; RXB0DB0 0x66 622 000768 3400 retlw 0x00 ; RXB0DB1 0x67 623 000769 3400 retlw 0x00 ; RXB0DB2 0x68 624 00076A 3400 retlw 0x00 ; RXB0DB3 0x69 625 00076B 3400 retlw 0x00 ; RXB0DB4 0x6A 626 00076C 3400 retlw 0x00 ; RXB0DB5 0x6B 627 00076D 3400 retlw 0x00 ; RXB0DB6 0x6C 628 00076E 3400 retlw 0x00 ; RXB0DB7 0x6D 629 00076F 3480 retlw 0x80 ; CANSTAT 0x6E 630 000770 3480 retlw 0x80 ; CANCTRL 0x6F 631 632 000771 3420 retlw 0x20 ; RXB1CTRL 0x70 Receive only Standard Id's that match Masks/Filters 633 END 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 648 ERRORS = 0, SRC CARDS READ = 1208