Unimacr os port map ( ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output
almost empty ALMOSTFULL => ALMOSTFULL, -- 1-bit output almost full DO
=> DO, -- Output data, width defined by DATA_WIDTH parameter EMPTY =>
EMPTY, -- 1-bit output empty FULL => FULL, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO
depth RDERR => RDERR, -- 1-bit output read error WRCOUNT => WRCOUNT,


FIFO_SYNC_MACRO #( 
	.DEVICE("7SERIES"), // Target Device: "7SERIES"
	//	.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
	//	.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
	.DATA_WIDTH(72), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE(="36Kb") 
	.DO_REG(0), // Optional output register (0 or 1)
	.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb" 
	)

FIFO_SYNC_MACRO_inst ( 
	.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit outputalmost empty 
	.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
	.DO(DO), // Output data, width defined by DATA_WIDTH parameter
	.EMPTY(EMPTY), // 1-bit output empty 
	.FULL(FULL), // 1-bit output full
	.RDCOUNT(RDCOUNT), // Output read count, width determined by FIfor depth 
	.RDERR(RDERR), // 1-bit output read error 
	.WRCOUNT(WRCOUNT), //Output write count, width determined by FIfor depth 
	.WRERR(WRERR), //1-bit output write error 
	.CLK(CLK), // 1-bit input clock 
	.DI(DI), //Input data, width defined by DATA_WIDTH parameter 
	.RDEN(RDEN), //1-bit input read enable 
	.RST(RST), // 1-bit input reset 
	.WREN(WREN) //1-bit input write enable
	);

