# 
# Synthesis run script generated by Vivado
# 

namespace eval rt {
    variable rc
}
set rt::rc [catch {
  uplevel #0 {
    set ::env(BUILTIN_SYNTH) true
    source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl
    rt::HARTNDb_resetJobStats
    rt::HARTNDb_startJobStats
    set rt::cmdEcho 0
    rt::set_parameter writeXmsg true
    rt::set_parameter enableParallelHelperSpawn true
    set ::env(RT_TMP) "./.Xil/Vivado-4254-dalham.cl.cam.ac.uk/realtime/tmp"
    if { [ info exists ::env(RT_TMP) ] } {
      file delete -force $::env(RT_TMP)
      file mkdir $::env(RT_TMP)
    }

    rt::delete_design

    set rt::partid xc7z020clg400-1
    source $::env(HRT_TCL_PATH)/rtSynthParallelPrep.tcl

    set rt::multiChipSynthesisFlow false
    source $::env(SYNTH_COMMON)/common.tcl
    set rt::defaultWorkLibName xil_defaultlib

    set rt::useElabCache false
    if {$rt::useElabCache == false} {
      rt::read_verilog -include /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_infrastructure_v1_1/cf21a66f/hdl/verilog -define {PYNQ20=1 DUT_WANTS_RESULT64_SERVICE=1 DUT_WANTS_NOC8_SERVICE=1} {
      /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/hpr_ipblocks/cvip0/cvgates.v
      /home/djg11/d320/hprls/kiwipro/kiwic/distro/lib/hpr_ipblocks/cvip0/cv_fparith.v
      /home/djg11/Dropbox/out/fir2d.v
      /home/djg11/vivado-cmdlines/ksubs3/ksubs3_axi_zynq/ksubs3_zynq_toplevel.v
      /home/djg11/vivado-cmdlines/ksubs3/ksubs3_axi_zynq/ksubs3_axi_pio_target.v
      /home/djg11/vivado-cmdlines/ksubs3/ksubs3_axi_zynq/ksubs3_innercore.v
      /home/djg11/vivado-cmdlines/ksubs3/membank_hf1.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/djgaxi_auto_pc_0/synth/djgaxi_auto_pc_0.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/djgaxi_processing_system7_0_0/synth/djgaxi_processing_system7_0_0.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/djgaxi_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_infrastructure_v1_1/cf21a66f/hdl/verilog/axi_infrastructure_v1_1_vector2axi.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_infrastructure_v1_1/cf21a66f/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_register_slice_v2_1/03a8e0ba/hdl/verilog/axi_register_slice_v2_1_axic_register_slice.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_register_slice_v2_1/03a8e0ba/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_aw_channel.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_cmd_translator.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_simple_fifo.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_decerr_slave.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v
      /home/djg11/vivado-cmdlines/ksubs3/xilinx_ip/djgaxi.v
    }
      rt::filesetChecksum
    }
    rt::set_parameter usePostFindUniquification false
    set rt::top ksubs3_zynq_toplevel
    set rt::reportTiming false
    rt::set_parameter elaborateOnly false
    rt::set_parameter elaborateRtl false
    rt::set_parameter eliminateRedundantBitOperator true
    rt::set_parameter writeBlackboxInterface true
    rt::set_parameter ramStyle auto
    rt::set_parameter merge_flipflops true
# MODE: 
    rt::set_parameter webTalkPath {./.Xil/Vivado-4254-dalham.cl.cam.ac.uk/wt}
    rt::set_parameter enableSplitFlowPath "./.Xil/Vivado-4254-dalham.cl.cam.ac.uk/"
    set ok_to_delete_rt_tmp true 
    if { [rt::get_parameter parallelDebug] } { 
       set ok_to_delete_rt_tmp false 
    } 
    if {$rt::useElabCache == false} {
        set oldMIITMVal [rt::get_parameter maxInputIncreaseToMerge]; rt::set_parameter maxInputIncreaseToMerge 1000
        set oldCDPCRL [rt::get_parameter createDfgPartConstrRecurLimit]; rt::set_parameter createDfgPartConstrRecurLimit 1
      rt::run_synthesis -module $rt::top
        rt::set_parameter maxInputIncreaseToMerge $oldMIITMVal
        rt::set_parameter createDfgPartConstrRecurLimit $oldCDPCRL
    }

    set rt::flowresult [ source $::env(SYNTH_COMMON)/flow.tcl ]
    rt::HARTNDb_stopJobStats
    rt::HARTNDb_reportJobStats "Synthesis Optimization Runtime"
    if { $rt::flowresult == 1 } { return -code error }

    if { [ info exists ::env(RT_TMP) ] } {
      if { [info exists ok_to_delete_rt_tmp] && $ok_to_delete_rt_tmp } { 
        file delete -force $::env(RT_TMP)
      }
    }


  set hsKey [rt::get_parameter helper_shm_key] 
  if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] && [info exists rt::doParallel] && $rt::doParallel} { 
     $rt::db killSynthHelper $hsKey
  } 
  rt::set_parameter helper_shm_key "" 
    source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
  } ; #end uplevel
} rt::result]

if { $rt::rc } {
  $rt::db resetHdlParse
  set hsKey [rt::get_parameter helper_shm_key] 
  if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] && [info exists rt::doParallel] && $rt::doParallel} { 
     $rt::db killSynthHelper $hsKey
  } 
  source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
  return -code "error" $rt::result
}
