Expression forms: Declarative Design using Atomic Actions

Parallel expression without threads is also possible: use a collection of state machines or Bluespec rules.

Examples:

• Statecharts (MARTE UML/SysML Synthesis).
• Bluespec System Verilog,

  rule allocate (!allocated);
     allocated <= True;
     owner <= currentRequestor;
  endrule;

Every operation has a guard predicate: says when it CAN be run

Operations have the expectation they WILL be run (fairness).

Scheduling decisions can span various power/performance issues without recoding.