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To: Ching-Tsun Chou <chou@CS.UCLA.EDU>
Cc: info-hol@leopard.cs.byu.edu, Richard.Boulton@cl.cam.ac.uk
Subject: Re: VHDL
In-Reply-To: Your message of "Mon, 25 Sep 1995 12:21:07 PDT." <199509251921.MAA20398@pelican.cs.ucla.edu>
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Date: Tue, 26 Sep 1995 09:39:58 +0100
From: Richard Boulton <Richard.Boulton@cl.cam.ac.uk>
Message-Id: <"swan.cl.cam.:081850:950926084016"@cl.cam.ac.uk>

Ching-Tsun Chou <chou@CS.UCLA.EDU> writes:

> Where can I get a copy of John Van Tassel's work on
> formalizing VHDL in HOL?

His PhD thesis can be found at URL:

   http://www.cl.cam.ac.uk/ftp/hvg/papers/JVTthesis/

> Also, are there other works on formalizing VHDL in
> other theorem provers?

Ralf Reetz <reetz@ira.uka.de> and Thomas Kropf at Karlsruhe have been working
on formalizing VHDL in HOL. The following paper contains a survey of related
work:

   R. Reetz and T. Kropf
   "A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL"
   Formal Methods in System Design, 7(1/2):73-99, August 1995.

In fact, that whole issue is devoted to VHDL semantics.

Richard.

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Richard J. Boulton, University of Cambridge Computer Laboratory,
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