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From: claesen@imec.be (Luc Claesen)
To: "info-hol@leopard.cs.byu.edu"@imec.be
Subject: CFP: ED&T'95 (EDAC - ETC - EUROASIC)

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              THE EUROPEAN DESIGN AND TEST CONFERENCE 1995

                          EDAC - ETC - EUROASIC


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                          EDAC - ETC - EUROASIC

              THE EUROPEAN DESIGN AND TEST CONFERENCE 1995

==============================================================================


                   CALL FOR PAPERS

         THE EUROPEAN DESIGN AND TEST CONFERENCE 1995

        EDAC                   ETC              EUROASIC
The European Conference      European       The European Event    
 on Design Automation     Test Conference    in ASIC Design        

                   Paris, France, March 6-9, 1995
Sponsored by the EDA Association and by the IEEE Computer Society

SCOPE OF THE CONFERENCE

The scope of the 1995 European Design and Test Conference covers that of the
originally separate conferences EDAC, ETC and EUROASIC. In the context of 
electronic and electromechanical products ranging from integrated circuits 
through multi-chip modules and printed-circuit boards to full systems it 
deals with:

1.    The actual design of such products.
      Emphasis is on challenges and experiences concerning the design of
      advanced electronic components and systems. 

2.    The entire field of Design Automation and tools for such products.
      Emphasis is on methods and tools employed in all aspects of the
      use of computers for designing products. This includes fully automatic
      as well as computer-guided approaches, data management techniques and
      user interfaces.

3.    Testing of electronic products. 
      This includes testing of digital, mixed digital/analogue and analogue
      circuits and systems, test program development, test systems and design 
      for testability.

The 1995 European Design and Test Conference is sponsored by
the EDA Association, a non-profit association of European DA professionals
and by the IEEE Computer Society. It is held in cooperation with 
the IEEE Circuits and Systems Society and other European Societies. 

AIMS:

The aim is to meet the much needed requirement for an international conference 
with a European flavour to provide a significant focus and forum for Electrical 
Engineering professionals. The intention is to establish a forum
for the presentation of outstanding industrial and academic technical work in
the above mentioned areas. The need for such a forum comes from the increasing
specialisation of application areas, which requires a closer link between 
Design, Testing and Design Automation. The 1995 joint event will give
the opportunity to designers and test engineers to exchange information and 
requirements on CAD, CAT and ATE, and to obtain information on the latest 
developments in all these areas. Panels, tutorials, fringe meetings, awards, 
and a University Booth will be part of the conference. In 1994, the joint 
conference had over 400 paper submissions from which international reviewers 
selected high-quality papers for presentation at the conference. This number of 
submission has made the joint conference the largest European event in its area.

EXHIBITION:

An Exhibition will be held from February 21 to February 23, 1995, in parallel 
with the conference, and will be open free of charge to all attendees. It is 
expected that over 80 exhibitors specialising in CAD, ASIC design, ATE and CAT
tools will participate. Those requiring exhibition space should contact the 
Exhibition Secretariat.

LOCATION:

The Conference & Exhibition will be held in the prestigious CNIT Conference
and Exhibition Centre, located in Paris-La Defense, near to La Grande Arche,
and only a 10 minute `metro' ride from downtown Paris.

INFORMATION:

Conference Secretariat:       Exhibition Secretariat:       
                                                            
 CEP Consultants Ltd          SEPIC                         
 26-28 Albany Street          1, Rue du Parc                
 Edinburgh, EH1 3QH, UK       92593 Levallois Perret        
 Phone: +44 31 557 2478       Phone: +33 (1) 49 68 54 58    
 Fax: +44 31 557 5749         Fax: +33 (1) 49 68 54 66      

General Chair:        A. Ambler
                      (e-mail: tony.ambler@brunel.ac.uk)
Vice-General Chair:   C. Lopez Barrio
Programme Chair:      P. Marwedel
                      (e-mail: marwedel@ls12.informatik.uni-dortmund.de)
Vice-Programme Chair: G. Saucier

DEADLINES AND KEY DATES:
Submission of Manuscripts                 September 7,     1994
Notification of Acceptance                November  3,     1994
Final version of manuscript due           December  7,     1994
Pre-Conference Tutorials                  March     6,     1995
Conference Sessions                       March     7-9,   1995
Exhibition                                March     7-9,   1995

AREAS OF INTEREST
Original technical papers on (but not limited to) the
following topis are invited:

1.    Full System Design:

      Actual industrial or academic designs, applications of E-CAD;
      consumer electronics, telecommunications,
      automotive electronics, computers, 
      electromechanical systems.  

2.    Digital ASIC and ASIP Design:

      Actual industrial or academic designs;
      design of advanced chips and chip-sets;
      experimentation with advanced CAD tools
      and methodologies; use of libraries.

3.    Mixed Digital/Analogue Design:

      Actual industrial or academic designs;
      use of tools for analogue or mixed digital/analogue design;
      library description management and characterisation.   

4.    System Design Technologies:

      Specification languages; system design techniques and tools; framework 
      technologies; partitioning; software-hardware codesign; code generation 
      for embedded processors; concurrent engineering, design modelling.

5.    Architectural Synthesis:

      Synthesis at the architectural level; high-level synthesis; architectural 
      trade-offs; performance and cost driven architectural synthesis; timing 
      and power issues.

6.    Logic and finite state machine synthesis:

      Combinational logic synthesis; technology mapping; hierarchical controller
      synthesis; state assignment; synthesis of testable controllers;
      performance driven synthesis and power control; PLD and FPGA synthesis; 
      timing issues.

7.    Simulation and Emulation:

      Advanced simulation techniques from systems to circuit level; simulation
      accelerators; simulation of mixed analogue-digital circuits; emulation
      techniques; embedded hardware-software simulation; emulation of large
      systems.

8.    Formal Verification:

      Formal techniques and methods for verification; design correctness; use of
      automatic theorem provers; symbolic manipulation; formal specification
      languages; transformational design; BDD's; Symbolic state-space 
      traversal techniques; practical applications of formal verification.

9.    Layout Synthesis and Verification for VLSI, Boards and MCMs:

      Automatic place and route; performance and power driven layout;
      analogue and digital cell layout rule checking and characterisation; 
      electrical verification; modelling and characterisation of on and off 
      chip interconnects; layout tools for microsystem design.

10.   Design for Testability:

      Ad-hoc methods; internal scan; macro test; boundary-scan; built-in self 
      test. testability synthesis; I_DDQ testability; Proven < 50 PPM DfT 
      schemes; Testability planning.

11.   Test Program Development Tools and Techniques:

      Pattern generation; test pattern generation for memories;
      fault simulation; expert systems;
      inductive fault analysis; languages and standards.

12.   Mixed-signal Test:

      Analogue test and testability, analogue macro test, test methods
      for ADC, DAC, PLLs and Filters, mixed-signal tester interfaces,
      mixed-signal DfT, 
      I_DDX testing for analogue.

13.   Component, MCM, Board and System Testing:

      ATE hardware and software; test-pattern application; fixturing;
      pin electronics; diagnostic techniques;
      VXI bus systems; I_DDQ-test-hardware;
      functional and structural approaches and safety-critical applications;
      1149.1, 1149.2, 1149.4, micro-computer based self-test.

SUBMIT MANUSCRIPTS TO:

Conference Secretariat:  For information:        
CEP Consultants Ltd.     phone: +44 31 557 2478 
26-28 Albany Street      fax: +44 31 557 5749   
Edinburgh, EH1 3QH, UK   

SUBMISSION OF PAPERS:

Two different categories of papers are distinguished:

1) Submissions for the formal proceedings:

Papers on design, CAD and test from a scientific perspective.
Full-length, unpublished papers which will be reviewed for their
scientific contents and, if accepted, included in the proceedings
published by IEEE. Contributions in this category are expected to
advance the current state-of-the art in design, CAD or test technologies.

Each submission should include nine stapled copies of the
complete manuscript including one cover page and one abstract page. 
Any submissions which are received by fax will not be processed.
The nine manuscript sets should each include:

A Cover Page stating the names, affiliations and addresses of all authors,
together with the identification, telephone and fax number of the principal
author, bearing in mind that communication for paper acceptance and mailing of 
the author kit will occur in November 1994. The cover page should also include
the following signed statement.

All appropriate clearances for the publication of this paper have been obtained,
and if accepted the author will prepare the final manuscript in time for
inclusion in the Conference Proceedings and will present the paper at the
Conference.

Title and Abstract Page stating the title of the paper, a 70 word abstract
indicating what is new and significant in the results presented, and an ordered
list of Key Words taken from the areas and topics listed under areas of 
interest. The complete draft of the paper including an outline of all 
illustrations and references not exceeding 12 pages 
(double spaced A4, font >= 12). The international review panel will give 
high preference to papers that, excluding
references, figures and tables, do not exceed 3000 words to clearly present the
work, methods, results, originality, significance, superiority and applications
of the techniques discussed. Excessively long contributions will be returned to
the authors. As far as possible, although there  will be an
opportunity to update the paper from an extended abstract, the submitted
manuscript should closely reflect the final paper as it will appear in the
Proceedings, which will be 5 pages, double column format.

2) Submissions for the User's Forum:

Papers on design, CAD and test from a user's or vendor's perspective.
In this category, submission of extended summaries of up to 1500 words
is sufficient. Submissions will be reviewed and, 
if accepted, published in a separate User's Forum volume.
Papers on the following areas are especially welcome for this category:
practical applications, case studies, tradeoff analyses, competitiveness of 
target technologies, risk evaluations, industrial products, economical ASIC 
feasibility studies, surveys, state-of-the-art presentations.

ASIC PRIZE:

Any paper submitted, for either of the two categories, describing the design of 
a manufactured ASIC is a candidate for the `ASIC Prize'.
ASIC Prizes will be attributed to papers describing the most original and 
practical experiences in ASIC design.

On your submission, please mention clearly, whether your paper is intended to 
be published in the formal proceedings or in the User's Forum volume.