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Subject: ACM International Workshop on Formal Methods in VLSI Design


************* REGISTRATION INFORMATION and ADVANCE PROGRAM *************


                        1991 International  Workshop  on
                          Formal Methods in VLSI Design
                             Jan 9-11, 1991, Miami


BACKGROUND

There is increasing interest, both in academia and industry,
in the application of formal methods to the design of
integrated systems.  Some of this interest has been
motivated by the urgency of improving the reliability,
testability and robustness of designs.  The aim of this
series of workshops is to bring together researchers
interested in the application of formal techniques to the
hardware design process.  The emphasis of this year's
meeting is to provide an opportunity for synergistic
interaction between researchers in ``traditional'' CAD and
those interested in formal approaches to design.

PROGRAM COMMITTEE

L. Berman (IBM), D. Borrione (Grenoble), R. Bryant (CMU), R.
Camposano (IBM), S. K. Chin (Syracuse), L. Claesen (IMEC,
European co-chair), S. Devadas (MIT), D. Dill (Stanford), H.
Eveking (TU Darmstadt), M. Fourman (Edinburgh), W. Hunt
(Computational Logic Inc.), K. Keutzer (AT&T), P. Prinetto
(Torino), A. Sangiovanni-Vincentelli (Berkeley),
P.A.Subrahmanyam (AT&T, Workshop Chair).

WORKSHOP FORMAT

The workshop will consist of overviews of major topics by leading
researchers, submitted and invited papers, poster sessions, and
discussion sessions.  The intent of the workshop (and its format) is
intended to encourage in-depth informal discussions among participants.

REGISTRATION INFORMATION: Included at the end of this message, after the
advance program.

======================== CUT HERE FOR ADVANCE PROGRAM ==========================


                        1991 International  Workshop  on
                          Formal Methods in VLSI Design
                             Jan 9-11, 1991, Miami

                               ADVANCE PROGRAM


Wednesday

8:00-8:30 Breakfast

Binary Decision Diagrams in CAD/Verification

8:30-9:15
        Symbolic Model Checking: 10**20 States and Beyond
        Ed Clarke, D. Dill, J. Burch, et al.
        Carnegie Mellon University & Stanford University

9:15-9:20       Introductory Remarks:  P. A. Subrahmanyam (AT&T Bell Labs)

9:20-9:30       Discussion/Coffee Break

Binary Decision Diagrams in CAD/Verification

9:30-10:00
        Testing Language Containment for w-Automata using BDD's
        Herve Touati, R.K. Brayton, R. Kurshan
        UC Berkeley & AT&T
10:00-10:30
        Symbolic Computation of the Valid States of a Sequential Machine: Algorithms and Discussions
        Olivier Coudert & J. C. Madre
        BULL Research, France

10:30-10:45     Discussion/Coffee Break

Theorem Proving & CAD
                        Chair: L. Claesen (IMEC)

10:45-11:30
        Theorem Proving & CAD:
        W. Hunt
        Computational Logic Inc, Austin

11:30-11:50
        VHDL Verification in the State Delta Verification System (SDVS)
        Ivan Filippenko
        The Aerospace Corp, Los Angeles

11:50-12:10
        One Aspect of Mechanizing Formal Proof of Hardware: the Generalization of Partial Specifications
        Laurence Pierre
        Universite de Provence, France

12:10-12:30 Discussion

12:30-2:00      LUNCH!

Hardware Design & Higher Order Logic
                        Chair: S.K.Chin (Syracuse University)

2:00-2:30
        The HOL Verification of ELLA Designs
        R.Boulton, M. Gordon, J. Herbert, J. V. Tassel
        University of Cambridge
2:30-2:50
        Extracting Circuits From Constructive Proofs
        David A. Basin
        University of Edinburgh
2:50-3:10
        A Methodology for Integrating Hardware Design and Verification
        S. Kalvala, Myla  Archer, Karl Levitt,
        University of California, Davis
3:10-3:30
        Abstract Hardware
        Phillip J. Windley
        University of Idaho, Moscow, Idaho

3:30-3:45:      Discussion/Coffee Break
3:45-4:15
        SFG-Tracing: A Methodology for the Automatic verification of MOS transistor level
        Implementations from Behavioral Signal Flow Graph Specifications
        L. Claesen
        IMEC, Belgium
4:15-4:45
        Discussion: Experiences using theorem proving for verification
        P. Lowenstein (Mitsubishi & Stanford):
                        Experiences Using A Theorem Prover for Hardware Verification
        Beth Levy (Aerospace Corporation):
                        An Overview of Hardware Verification Using the State Delta Verification System
        Jeff Joyce (Univ. British Columbia):
                        More Reasons Why Higher-Order Logic is a good
                        Formalism for Specifying and Verifying Hardware

4:45-5:00       General Discussion

Wednesday Evening: Reception

7:00-9:30       Poster Presentations and Discussion
                [Posters will be on display through Friday]



Thursday

8:00-8:30:      Breakfast

CAD + Finite State Machine Equivalence
                        Chair: K. Keutzer (AT&T Bell Labs)

8:30-9:00
        Model Checking in CAD
        R. Kurshan
        AT&T Bell Labs
9:00-9:30
        Comparison of non-deterministic finite state automata
        Eduard Cerny, R. Rioux
        Univ. de Motreal
9:30-10:00
        Behavior FSMs for High-Level Verification and Synthesis
        Miriam Leeser, Wayne Wolf
        Cornell Univ. & Princeton Univ.
10:00-10:30     Discussion/Coffee Break

Finite State Machines - II
                        Chair: S. Devadas (MIT)
10:30-11:00
        Quotient and Isomorphism Theorems of a Theory of Sequential Hardware Equivalence
        Carl Pixley & G. Beihl
        MCC, Austin, Texas

11:00-12:00
        Panel Discussion: Model Checking, Theorem Proving & CAD
                Kurt Keutzer (AT&T), Alberto Sangiovanni-Vincentelli (UCBerkeley), L. Berman (IBM), others
12:00-12:30     General Discussion

12:30-2:00 Lunch

Timing Issues in Design
                Chair: D. Dill (Stanford)
2:00-2:30
                The Formal Description and Verification of Hardware Timing
        G. Milne
        Univ. of Strathclyde, Scotland
2:30-2:50
        Timing Validation of Hardware Descriptions
        N. Awad,J.  Lin,  R. Sathianathan, D. Smith
        SUNY Stony Brook
2:50-3:10
        On Deducing Un-specified Constraints from Timing Specifications
        F. Mavaddat, T. Gahlinger
        U. Waterloo
3:10-3:30
        Weakening the Weak Conditions for Self-Timed Circuits
        Manfred Broy, Carlos Delgade Kloos
        TU Munich, (Germany) & Univ. Madrid (Spain)

3:30-4:00:      Discussion/Coffee Break

Synthesis and Verification
        Chair: L. Berman (IBM)
4:00-4:30
        A Practical Application of Verification to High Level Synthesis
        Michael C. McFarland
        Boston University

4:30-5:00
        Some Commentary on Hardware Design with Mixed Integer Linear Programming
        Lou Hafer
        Simon Fraser University, Canada

5:00-5:30
        Verification of synchronous Sequential Circuits Obtained from Algorithmic Specifications
        F. Corella, R. Camposano, R. A. Bergamaschi, M. Payer
        IBM Research, Yorktown Heights, NY

Thursday Evening:       Banquet!!!

Friday Morning

8:00-8:30:      Breakfast

Algebraic Techniques for Design
        Chair: G. Milne (University of Strathclyde)

8:30-9:00
        DDD- A system for mechanized Digital Design Derivation
        Steven D. Johnson & B. Bose
        Indiana University

9:00-9:30
        A Hardware Implementation of Pure Esterel
        G. Berry
        Ecole des Mines, Sophia-Antipolis  & DEC Research, Paris (France)

9:30--9:50
        HINTS: A Hardware Interpretation System
        Y. T Lai & Sarma Sastry
        Univ. Southern California

9:50-10:15:     Discussion/Coffee Break

10:15-11:15     Panel: What did we learn? And where do go from here?
                        Moderator: P. A. Subrahmanyam (AT&T Bell Labs)

11:15-12:30

Potpourri
        Chair: P.Prinetto (Torino)

11:15-11:30
        The Symbolic Manipulation of Event Traces
        Tony Larsson
        Linkoping University, Sweden

11:30-11:45
        Decidable and Undecidable Problems in Systolic Circuit Verification
        Parosh Abdulla
        Uppsala University, Sweden

11:45-12:00
        An Example of Interactive Hardware Transformation
        Zheng Zhu & S. Johnson
        Indiana University


Wednesday: 7:30-9:30    Posters & Discussion

BDDs
        Implicit Computation of Extended Sequential Don't Care Sets Using BDD's
        Bill Lin & R. Newton
        UC Berkeley

CAD & Theorem Proving

        Verifying a Delay Insensitive Fair Arbiter with the Boyer-Moore Prover
        David Goldschlag
        Computational Logic Inc., Austin

        A Formal Specification and Verification of a  Floating-Point Coprocessor
        based on MC68881 and its Composition with the Central Processing Unit
        Jing Pan, K. N. Levitt, E. T.  Schubert
        University of California, Davis

        Higher-Order Metafunctions for Synthesizing Signed-Binary Arithmetic hardware
        Shiu-Kai Chin
        Syracuse University


Timing Issues

        Tight Structural Timing Constraints for Level-Clocked Circuits
        Alexander T. Ishii
        Massachussetts Institute of Technology

        Timing Verification of Logic Circuits
        Peter P.K. Chiu & Y.S.Cheung
        Univ. of Hong Kong

        A Restricted Calculus for the Specification of Timing Behavior
        Tod Amon, G. Boriello
        Univ. of Washington

Integrating Hardware Design and Verification

        Integrating Hardware Verification with Design Automation
        S. Rajgopal, Kye Hedlund, D. Reeves
        Univ. North Carolina, Chapel Hill & NC. State

        uSPEED: a framework for Specifying and Verifying Microprocessors
        D. Borrione, H. Colvizza, C. Le Faou
        Univ Joseph Fourier, IMAG, Grenoble & Uni. Provence, Marseille (France)

Systolic Arrays

        On  One-Dimensional Systolic Arrays
        J. Xue & C. Lengauer (Univ. of Edinburgh)

        Specification of Real-Time Broadcast Networks
        Pradeep Jain & Simon Lam
        Univ. Texas, Austin

Algebraic Techniques in Design and Simulation

        Symbolic Analysis of Digital CMOS Networks Using Distributive Lattices
        Michael Payer
        IBM Research, Yorktown Heights, NY

        An Algebraic Model for Datapath Design Space Exploration
        Akhilesh Tyagi
        University of North Carolina, Chapel Hill

        Process Algebras in Design and Analysis
        G. Milne  et al.
        Univ. of Strathclyde, Scotland

        Formal Functional Verification of Hardware Designs
        Zmago Brezocnik & B. Horvat
        Univ. of Maribor, Yugoslavia

==================================================================================

-----------------------------------------------------------------------

LOCAL INFORMATION

The workshop will be held at the Omni Intertation Hotel overlooking
Biscayne Bay, conveniently located downtown, 10 minutes from Miami
International Hotel ($8-$12 taxi ride).  The Hotel is situated just
across from the Miami Area and Bayside Marketplace.  The rooftop pool
overlooks the downtown skyline and Biscayne Bay.  The Omni also provides
shuttle service for hotel guests to South Beach in Miami Beach.

Ths sunny South Florida location, with warm tropical breezes, allows
visitors to enjoy year-round outdoor activities, such as sailing,
swimming, and fishing.  Golf and tennis are two other activities within
minutes of the Omni's front door.  A unique shopping experience can be
found in a multitude of areas.

HOTEL REGISTRATION

A reduced winter hotel rate of $92 has been negotiated for Workshop
participants.  To make your jotel reservations call the Omni at
305-374-0000 and refer to ACM/VLSI'90.


WORKSHOP REGISTRATION

The registration fee includes:

Continental breakfasts and coffee breaks on Wednesday, Thursday and Friday
Lunch on Wednesday and Thursday
Reception with complimentary hors d'ouvres (cash bar) on Wednesday evening
Banquet on Thursday evening
Conference Proceedings

---------------------------cut here for registration form-------------------

                        ACM/VLSI'90 Advance Registration Form
                          January 9-11, 1991, Miami, Florida.

First Name:______________________ Last Name:______________________
Company/Institution:______________________________________________
Address:__________________________________________________________
__________________________________________________________________

Country:__________________________________________________________
PHONE/FAX:________________________________________________________

Circle Fee              Before December 8, 1990         After December 8, 1990

ACM/SIGDA Member        $295                            $325
Non-member              $325                            $375
Student                 $150                            $150

ACM Member # ________________________________
Student registration must be accompanied by a copy of a valid student
ID.

Additional Wednesday Reception Tickets: #Tickets___ X $15 = __________
Additional Banquet Tickets:             #Tickets___ X $30 = ___________

Payment Form (Circle one)       AMEX    MasterCard      Visa    Check
Credit Card #:____________________________________ Exp Date: ___________

Signature:______________________________________________________________

Send Registration to:

ACM/VLSI'90 Registration, ACM, 11 West 42nd Street, New York, New York,
NY 10036, Attn: Marcela Brathwaite.

If paying by credit card, you may fax the registration form to Marcel
Brathwaite at 212-302-5826.

Cancellations for refunds must be in writing, and received at ACM by
Marcela Brathwaite by Dec 15, 1990.

For registration information contact: Marcela Brathwaite, ACM,
212-869-7440 extension 347, e-mail: Marcela@acmvm.bitnet.

-------------------------cut here for registration form-------------------

PLEASE NOTE: The conference location has been moved to Biscayne Bay
(Miami) at the Omni International Hotel because ACM was unable to locate
reasonably priced (but good) accomodations in Puerto Rico (the
conference location announced earlier) for our time slot.  January is a
tourist season for the general area, and the Hotel that ACM was dealing
with unfortunately did not come through with their negotiations.  On the
positive side, the move to the viscinity of Miami also facilitates
travel for many (particularly from Europe, since Miami has an
international airport; the fares into Miami should also be somewhat
lower.) It is hoped that the location change will not affect your
decision to participate in the workshop!



