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Lecturer: Mr I.A. Pratt
(iap10@cl.cam.ac.uk)
No. of lectures: 8
Prerequisite course: Computer Design
- Comparing architectures.
- The technology curve. System versus chip performance. Speed:
MIPS, MHz, FLOPS, SPEC. Power. Price. Compatibility.
Features. [1.5 lectures]
- Instruction set architecture.
- Amdahl's law and RISC principles. Byte sex. Word size. Stacks,
Accumulators and GPRs. Load-store versus
register-memory. Addressing modes. Code density. Sub-word and
un-aligned loads and stores. [2 lectures]
- Pipelining.
- The CPU performance equation. Structural hazards: long latency
instructions. Data hazards: result forwarding and delayed loads.
Control hazards: optimising branches, and avoiding branches.
Exceptions. [2 lectures]
- Instruction level parallelism.
- Super-scalar. Static scheduling and dynamic out-of-order execution.
Register renaming. The limits of ILP. [1.5 lectures]
- Memory hierarchy.
- Cache configurations. Latency versus bandwidth. Re-ordering
and coherence. Programming for caches.
Highly recommended reading:
Hennessy, J. & Patterson, D. (1996). Computer Architecture: a
Quantitative Approach (Chapters 1-5 in particular). Morgan Kaufmann
(2nd ed.).
Further reading and reference:
Tannenbaum, A.S. (1990). Structured Computer Organization.
Prentice-Hall (2nd ed.).
Van Someren, A. & Atack, C. (1994). The ARM RISC Chip: a
Programmer's Guide. Addison-Wesley.
Sites, R.L. (ed.) (1992). Alpha Architecture Reference Manual.
Digital Press.
Kane, G. & Heinrich, J. (1992). MIPS RISC
Architecture. Prentice-Hall.
Messmer, H. (1995). The Indispensable Pentium Book.
Addison-Wesley.
The CPU Info Center http://infopad.eecs.berkeley.edu/CIC/tech/
Next: Specification and Verification I
Up: Lent Term 1999: Part
Previous: Natural Language Processing
Christine Northeast
1998-10-01