Structured Hardware Design (50% option only)

Lecturer: Dr D.J. Greaves (djg@cl.cam.ac.uk)

No. of lectures: 6

This course is a prerequisite for the Group Project (Part IB) and for Introduction to VLSI (Part II).

Building blocks for digital electronics & HDL.

D-type, clock enable, broadside register, ROM, RAM, ALU, microprocessor.

Clocking and synchronous FSM combination.

Finite state machines: Mealy, Moore, composition and pipelining. Decomposition. Set and hold times, clock skew. FSMs on different clocks. Asynchronous boundaries. Gated clocks.

Technology, speed, power, gate delays.

Capacitance, inductance, resistance, speed of light. Model of a gate, derating of a model with load and temperature. Delay-power product. Model of a net. Back-annotated net delay. IO pads and PCB tracks. Modular design, libraries and design partition: Standard parts, ASICs, PALs and FPGAs. [2 lectures]

Hardware versus software.

Processor speed, hardware speed, design reuse, full custom versus semi-custom, bit serial logic, microcode, embedded systems, ROM and processor on the same chip.

Further circuit structures and examples.

Recommended book:

Floyd, T.L. (1997). Digital Fundamentals. Prentice-Hall.