Comparative Architectures

Lecturer: Mr I.A. Pratt (iap10@cl.cam.ac.uk)

No. of lectures: 8

Prerequisite courses: Processor Architecture, Computer Architecture  

Comparing architectures.

The technology curve. System versus chip performance. Speed: MIPS, MHz, FLOPS, SPEC. Power. Price. Compatibility. Features.

Instruction Set Architecture.

Amdahl's law and RISC principles. Byte sex. Word size. Stacks, Accumulators and GPRs. Load-store versus Register-memory. Addressing modes. Code Density. Sub-word and un-aligned loads and stores.

Pipelining.

The CPU performance equation. Structural hazards: long latency instructions. Data hazards: result forwarding and delayed loads. Control hazards: optimizing branches, and avoiding branches. Exceptions.

Instruction level parallelism.

Super-scalar. Static scheduling and Dynamic out-of-order execution. Register renaming. The limits of ILP.

Memory hierarchy.

The cache equation. Hiding latency. Re-ordering and coherence. Programming for caches.

Highly recommended reading:

Hennessy, J. & Patterson, D. (1996). Computer Architecture: a Quantitative Approach (Chapters 1-5 in particular). Morgan Kaufmann (2nd ed.).

Further reading and reference:

Tannenbaum, A.S. (1990). Structured Computer Organization. Prentice-Hall (2nd ed.).

Van Someren, A. & Atack, C. (1994). The ARM RISC Chip: a Programmer's Guide. Addison-Wesley.

Sites, R.L. (ed.) (1992). Alpha Architecture Reference Manual. Digital Press.

Kane, G. & Heinrich, J. (1992). MIPS RISC Architecture. Prentice-Hall.

Messmer, H. (1995). The Indispensable Pentium Book. Addison-Wesley.

The CPU Info Center http://infopad.eecs.berkeley.edu/CIC/tech/