Structured Hardware Design (50 per cent only)

Lecturer: Dr D.J. Greaves (djg@cl.cam.ac.uk)

No. of lectures: 6  

Combinatorial & Register Transfer Design using schematics & HDL.

D-type, clock enable, broadside register, ROM, RAM, ALU, microprocessor.

Synchronous logic.

Finite state machines - Mealy, Moore, Composition and pipelining. Decomposition. Set and hold times, clock skew. FSMs on different clocks. Asynchronous boundaries. Gated clocks.

Modelling, speed and power.

Capacitance, inductance, resistance, speed of light. Model of a gate, derating of a model with load and temperature. Delay-power product. Model of a net. Back-annotated net delay. IO pads and PCB tracks.

Hardware versus software.

Processor speed, hardware speed, design reuse, full custom versus semi-custom, bit serial logic, microcode, imbedded systems, ROM and processor on the same chip.

Modular design, libraries and design partition.

Standard parts, ASICs, PALs and FPGAs.

Worked design example.

Recommended book:

Floyd, T.L. (1997). Digital Fundamentals. Prentice-Hall.