
Tenison Technology PU17 processor, Technical Spec (C) 1999 TenisonTech.  


This is a general purpose processor with 16 bit register to register
operations and byte and word (16bit) memory operations.  There are 8
data registers and a PC. The data registers are mainly orthogonal, except
that only R0-3 and R7 may be used for indexing and R6 is used for the
link in a branch and link instruction.

                  8 general purpose registers of 16 bits, A16, D16.
                  0-3, 7 can be used as index registers
                  6 is link register
                  7 is base for LDM,STM

The main addressing modes are register, absolute 16, immediate 8 and
indexed where the offset is a 6 bit positive value giving even values
from 0 to 126.  There is also a 16 bit load immediate. The machine is
LITTE ENDIAN so that even values are not a penalty in C compiled code.

All instructions are either 2 or 4 bytes long.

Subroutine link is through branch and link with R6 being the
link register.  

R7 is the index register used for load and store multiple and hence
is normally used as the stack pointer.  Registers are stored
or loaded from the address pointed to by R7, which must be even, upwards.
R7 is not changed by LDM/STM unless it is a destination for LDM.


Conditional branches are relative or absolute and use the standard
conditions on the NZCV flags.

Reset is to address 0.

No interrupts at the moment.


The current calling method does not use LDM/STM.  This will be
used in the enhanced version.

OPCODE
---------------------------------------------------------------------------
0-7     0xxx.   R3DEST, ALU4, IMMED8	   		: Imm 8 bit 
                     7,    3,  14-10, 2-0
---------------------------------------------------------------------------
8-B 	10xx.	 BYTEF, STOREF,   IDXR2, REG3,  IDX7,   : Indexed load/stores/add/sub
                   13,      12,   10,    7,       0    : 
---------------------------------------------------------------------------
C	1100.	COND4, OFFSET8				: Relative branches + bsr
                    8        0 
---------------------------------------------------------------------------
D0	1101.00	R3DEST, ALU4, R3SRC	   		: ALU reg,reg ops
                     7     3      0
---------------------------------------------------------------------------
D4	1101.01	REG3, BYTEF1,  STOREF, ABS16		: Abs16 load/store
                   7       6        5,  next
---------------------------------------------------------------------------
D8	1101.10 COND4, ABS16				: Absolute jmp jsr   
                    2,
---------------------------------------------------------------------------
DC      1101.11 RLIST8 STOREF                           : Load/store multiple
                     2,     1                           : Upwards from R7, r7 not changed
---------------------------------------------------------------------------
F0	1111.00 REG3 	LinkF				: Branch indirect 
	           7,       0                           : bx, bxl
---------------------------------------------------------------------------
F4      1111.01 REG3, Immed16				: Load immediate (mov special case)
                   7

//
//  V6, V8 and V16 are constant fields of that width in bits.
//  hash (#) denotes immediate addressing.  0x for hex numbers.
//
//  ALU code f: 0:str 1:add 2:sub 3:addc 4:subc 5:cmp 6:or 
//              7:and 8:xor 9:asl/lsl 10:lsr 11:lsr 12:arg  13:tst  
//

Conditional jump conditions are as follows.  Condition 15 means unconditional
branch and link in the absolute version and should not be used in the
relative version.
	cc: 0:EQ 1:NE 3:LT 3:GE 4:GT 5:LE 6:C 7:NC 8:V 9:NV 10:ALWAYS 
            11:HI 12:LS 13:MI 14:PL  15:SUB

//  Return is branch indirect on R6.

//  The assembler supports jcc and bcc, where jcc forces 16 bit mode.

//  The offset in relative jumps is the offset from the instruction divided by 2.
//  For bsr, the offset is from the next instruction ??



C linkage

R7 is the base register for C compiled code.  Args 0 and 1 are passed
in registers 0 and 1 with the result being in R0 (or R0low, R1high
if a long (32 bits)).



TODO:  bxl calling nested function args


Notes:

It is easy to confuse load and move both at the assembly level
and on the ALU function code level.  At the assembler level, strictly
speaking, a load should be used for memory fetches and a move from
other registers.  The assembler might be generous and fix up occasional
uses of the wrong instruction since the context is clear.

At the function code level, FC=0 is used for a move and FC=12

For the calling convention for C linkage, see targetpu.h in the C compiler.

END

(C) 1999 TenisonTech

