Transient faults are becoming more of a problem to processor designers as feature sizes shrink and the number of transistors on a chip increases. Significant research has focused on hardware techniques to evaluate and reduce the architectural vulnerability to soft errors (AVF). This paper, however, considers the problem from a different angle, evaluating the effects of compiler optimisations on the AVF of an entire embedded processor. We consider the impact on performance and AVF and produce a new metric (ADS) to evaluate the trade-offs between reducing susceptibility to transient faults and decreasing processor performance. We show that optimisations enabled by default at -O2 and -O3 can lead to large performance decreases, a higher AVF value and an ADS value of over 1.2. However, selectively picking the combination of optimisations means that performance increases can be achieved with negligible effect on AVF, leading to an ADS value of 0.91, with the best combination reducing one benchmark’s AVF by 13%.