Research

I am a PhD student at the Computer Architecture Group. I'm supervised by Dr. David Greaves. I'm interested in developing compilers for implementing unrestricted, unmodified high-level language code as custom-computation, particularly on coarse-grained reconfigurable or 'spatial' hardware.

Thanks to the growing ubiquity of portable computers, computer architects are faced with increasingly constrained power budgets. Furthermore, given that on-chip power density scaling trends are no longer sustainable, only a fraction of future chips' resources can be powered at any given time [1]. Thus, in order to continue scaling performance with Moore's law, achieving high energy efficiency has become essential. As a result, designers are increasingly utilising custom-computation to accelerate embedded applications, often as part of heterogeneous systems-on-chip. Custom-computing is also increasingly utilised in the HPC domain via reconfigurable architectures (e.g. FPGAs), to provide high performance and energy-efficiency without compromising generality.

Despite the advantages of custom (or reconfigurable) computing, there are two key issues that hinder the utilization of this approach for general-purpose computation. Amenability: So far, custom computing has ony been suitable for applications, with simple, regular control-flow and abundant (data) parallelism. Irregular applications with complex, data-dependent control flow achieve higher sustained performance on conventional, out-of-order superscalar processors with their support for aggressive control-flow speculation. Productivity: implementing computation as custom hardware often requires the use of low-level HDLs such as Verilog or VHDL. While several high-level synthesis tools do exist for generating hardware from high-level languages like C or C++, they often require that only a subset of the language be used, excluding features such as recursion, object-oriented programming, dynamic memory allocation etc. that are important for programmer productivity.

Both of these issues hinder the custom implementation of the vast amounts of legacy code in the general-purpose application domain. For my PhD, I'm working on developing a compiler intermediate representation that statically exposes greater ILP even in the presence of complex control-flow. Using this representation, I aim to address the amenability problem by improving the custom computing performance of control-flow intensive code, enough to at least match (if not exceed) conventional processors.

Furthermore, my compiler is based on the LLVM infrastructure - I use the LLVM-IR as input to my compiler, generating an equivalent Bluespec SystemVerilog implementation of the input code. I hope to address the productivity problem in this manner, as any HLL language that has an LLVM front-end could theoretically be compiled down to custom hardware using my compiler.

Stay tuned for updates...

Background

I received an MS degree in Computer Engineering from the King Fahd University of Petroleum & Minerals (KFUPM), Dhahran, KSA, in 2007. Earlier, I received a B.Eng. degree (First Class) in Computer Systems Engineering from NED University of Engineering and Technology, Karachi, Pakistan, in 2001.

In previous years I have worked at the Information Technology Center at KFUPM, primarily on setting up KFUPM's High Performance Computing Facility. I have also served as Lecturer at the Electronic Engineering department at Iqra University, Karachi.

During my MS studies, my research focused on the parallelization of stochastic heuristics, particularly Simulated Annealing, Simulated Evolution, and Genetic Algorithms. I have co-authored several publications from this work.

Publications

Journal Papers:

Sadiq M. Sait, Mustafa I. Ali and Ali Mustafa Zaidi, Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement, Journal of Mathematical Modelling and Algorithms (JMMA), pp. 433-454, Volume 6, Number 3, Springer Netherlands, September 2007. PDF.
Sadiq M. Sait, Ali Mustafa Zaidi and Mustafa I. Ali, Exploring Asynchronous MMC Based Parallel SA Schemes for Multiobjective Cell-Placement on a Cluster of Workstations , Arabian Journal for Science and Engineering, pp. 259-278, Volume 36, Number 2, accepted December 2009. PDF.

Conference Papers:

Sadiq M. Sait, Ali Mustafa Zaidi and Mustafa I. Ali, Asynchronous MMC based Parallel SA Schemes for Multiobjective Standard Cell Placement, IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos, Greece, May 2006. PDF
Sadiq M. Sait, Mustafa I. Ali and Ali Mustafa Zaidi, Evaluating Parallel Simulated Evolution Strategies for VLSI Cell Placement, IEEE International Symposium on Parallel and Distributed Processing (IPDPS 2006), Rhodes Island, Greece, April 2006. PDF
Sadiq M. Sait, Syed Sanaullah, Ali M. Zaidi and Mustafa I. Ali, "Comparative Evaluation of Parallelization Strategies for Evolutionary and Stochastic Heuristics", Genetic and Evolutionary Computation Conference (GECCO-2005), Washington, D.C. USA, June 2005. PDF
Sadiq M. Sait, Mustafa I. Ali and Ali M. Zaidi, "Multiobjective VLSI Cell Placement using Distributed Simulated Evolution Algorithm", IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan, May 2005. PDF

Theses, Reports and Dissertations:

MS Thesis: "A Modular Reconfigurable Architecture for Asymmetric and Symmetric-Key Cryptography".
    Committee Chair: Dr. Alaaeldin A. M. Amin;
    Co-Chair: Dr. Sadiq M. Sait;
    Committee Members: Dr. Ahmad A. Al-Yamani, Dr. M. E. S. El-Rabaa, Dr. Adnan Gutub
View Abstract    Defense Presentation     Thesis

Contact

Ali Mustafa Zaidi
University of Cambridge
15 JJ Thomson Avenue
Cambridge CB3 0FD
United Kingdom

Ali-Mustafa.Zaidi AT cl DOT cam DOT ac DOT uk