My research interests lie in the general area of computer architecture and VLSI design. Some current and past research projects are highlighted below.
I also have a strong interest in general-purpose multicore processors and the challenges they present. I explore many of these issues in a recently completed MPhil course entitled Chip-Multiprocessors.
Programmable Fabrics and Spatial Compilers ( Loki )
This new project builds upon our experience of designing on-chip networks. The aim is to explore a broad range of interesting massively-parallel single-chip architectures that place the network at the heart of their design. Our simple cores are far more deeply interconnected to each other than traditional designs, sharing some similarities to FPGAs. The network is also free to carry both instructions and data between cores allowing individual cores to be exploited in a variety of interesting ways. We are pursuing work at both the architecture and circuit levels, together with the development of new compilation tools.
Daniel Bates, Alex Bradbury, Andreas Koltes and Nial Murphy are currently pursuing their PhDs in this area with me. There are currently research opportunities in this area for potential PhD students.
On-Chip Interconnection Networks
My work on interconnection networks has focused on developing low-latency and low-power on-chip routers. Initial work exploited speculation to produce the first single-cycle on-chip router [ISCA paper].
The approach was evaluated by fabricating a test chip (with support from Andrew West) containing 16 programmable traffic generators interconnected by a chip-wide packet switched network (4x4 mesh). The network employed virtual-channel flow-control with four virtual-channels per physical channel [DAC paper]. The approach still remains competitive today.
In 2006 I was invited to contribute (see Session 5 for slides and video) to an NSF sponsored workshop on interconnection networks for multicore systems. The workshop aimed to identify the key challenges that must be overcome in order to fully exploit on-chip networks. The conclusions are presented here.
I am the primary author of Netmaker. This is a freely available library of fully-synthesizable and parameterizable on-chip routers. This library contains full implementation details of many of the microarchitectural techniques we have explored. The library has been downloaded hundreds of times and is being used by various groups internationally for teaching and research. Uses include on-chip network and multicore performance experiments, power-estimation, thermal modelling and formal verification of on-chip router implementations.
Novel Approaches to System-Timing
As a research associate I helped design and implement a range of novel low-power asynchronous processors for embedded applications. This work was undertaken in collaboration with AT&T, Cambridge Consultants, and other members of the Rainbow Research Group. The culmination of this work was the fabrication of the Northport and Springbank test chips (see picture left).
Research undertaken at this time also explored the use of dual-rail asynchronous logic as a defence against side-channel analysis attacks. Dual-rail logic is now often seen in commercial smartcards to prevent data-dependent power emissions from leaking secret information.
A particular interest of mine has also been the design of pausible, stoppable, and data-driven local clocks. These have many applications including the clocking of on-chip interconnection networks. Many of these ideas are summarised in a recent survey paper and Chapter 9 of Prof. Kinniment's book on Synchronization and Arbitration in Digital Systems.