.\" NOTE: This bibliography has been translated automatically .\" from a bibtex source by bibtex2refer. .\" It is not guaranteed in any way. .\" Doug Arnold, May 1995 .\"{ ==================================================================== } .\"{ ==================================================================== } .\"{ } .\"{ On-Chip Network Bibliography } .\"{ } .\"{ BibTeX database file } .\"{ } .\"{ Robert D. Mullins } .\"{ Computer Laboratory, University of Cambridge } .\"{ 2007 } .\"{ } .\"{ ==================================================================== } .\"{ ==================================================================== } %L %B Interconnect-Centric\0Design\0for\0Advanced\0SoC\0and\0NoC %T A Brunch from the Coffee Table -- Case Study in NoC Platform Design %L Ahonen:2004:ABF %D 2004 %I Kluwer Academic Publishers %P 425-453", %E J. Nurmi, H. Tenhunen and A. Jantsch %A Tapani Ahonen %A others %B Proc. 6th International Workshop on System Level Interconnect Prediction %T Topology Optimization for Application-Specific Networks-on-Chip %L Ahonen:2004:TOF %D 2004", %C Paris, France %A Tapani Ahonen %A David Sigu\*:enza Tortosa %A Jari Nurmi %B nocs %T On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus %L Ainsworth:2007:OCP %D 2007", %A Thomas Ainsworth %A Timothy Pinkston %T Implementation of a 2x2 NoC with Wishbone Interface %L Akerlund:2005:IOA %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Daniel \AAkerlund %B 12th IEEE Intl. Symp. on Asynchronous Circuits and Systems (ASYNC'06) %T Multiple-Rail Phase-Encoding for NoC %L Alessandro:2006:MRP %D 2006 %P 107-116 %A Crescenzo D'Alessandro %A Delong Shang %A Alex Bystrov %A Alex Yakovlev %A Oleg Maevsky %B Proc. The 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03) %T Implementation of Interface Router IP for Proteo Network-on-Chip %L Alho:2003:IOI %D 2003", %C Poznan, Poland %A Mikko Alho %A Jari Nurmi %B Proc. The 1st Northeast Workshop on Circuits and Systems NEWCAS %T Switch-Based Interface Router IP for Proteo Network-on-Chip %L Alho:2003:SBI %D 2003", %C Montreal, Canada %A Mikko Alho %A Jari Nurmi %B Proc. of the 17th Intl. Conf. on Microelectronics (ICM) %T Considerations for fault-tolerant network on chips %L Ali:2005:CFF %D 2005", %A M. Ali %A M. Welzl %A M. Zwicknagl %A S. Hellebrand %N 02 %J IEE\0Proceedings\0Computers\0and\0Digital\0Techniques %T Asynchronous\0On-Chip\0Networks %L Amde:2005:AOC %D 2005 %V 152 %A M. Amde %A T. Felicijan %A A. Efthymiou %A D. Edwards %A L. Lavagno %T AMBA Bus Emulation in the Nostrum NoC using Best Effort Communication %L Andrzejewski:2005:ABE %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Marek Andrzejewski %B In Proc. Design, Automation and Test in Europe (DATE) %T Contrasting a NoC and a traditional interconnect fabric with layout awareness %L Angiolini:2006:CAN %D 2006", %A F Angiolini %A L Benini %A P Meloni %A L Raffo %A S Carta %B Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis %T Multi-objective Mapping for Mesh-based NoC Architectures %L Ascia:2006:MMF %D 2004 %C Stockholm, Sweden %P 182-187 %A Giuseppe Ascia %A Vincenzo Catania %A Maurizio Palesi %B Fourth IEEE Workshop on Embedded Systems for Real Time Multimedia %T Neighbors-on-Path: A New Selection Strategy for On-Chip Networks %L Ascia:2006:NOP %D 2006 %C Seoul, Korea %P 79-84 %A Giuseppe Ascia %A Vincenzo Catania %A Maurizio Palesi %A Davide Patti %B EMSOFT '05: Proceedings of the 5th ACM international conference on Embedded software %T Centralized End-to-End Flow Control in a Best-Effort Network-on-Chip %L Avasare:2005:CEF %D 2005 %C New York, NY, USA %I ACM Press %P 17-20 %A P. Avasare %A V. Nollet %A J-Y. Mignolet %A D. Verkest %A H. Corporaal %B Proceedings of the 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers %T Exploring\0the\0Design\0Space\0for\03D\0Clustered\0Architectures %L Awasthi:2006:ETD %D 2006", %P %A M. Awasthi %A R. Balasubramonian %J IEEE Micro special issue on Design and Test of System on Chip %T CHAIN:\0A\0Delay\0Insensitive\0CHip\0Area\0INterconnect %L Bainbridge:2002:CAD %D 2002", %V 142, No.4. %P 16-23 %A W. J. Bainbridge %A S. B. Furber %B \0Proceedings\0of\0the\09th\0IEEE\0Intl\0Symp.\0on\0Asynchronous\0Circuits\0and\0Systems %T \0Delay-Insensitive,\0Point-to-Point\0Interconnect\0using\0m-of-n\0codes %L Bainbridge:2003:DIP %D 2003 %A W. J. Bainbridge %A W. B. Toms %A D. A. Edwards %A S. B. Furber %P 132-140 %B Proceedings of the Design, Automation and Test in Europe Conference and Exhibition %T The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip %L Bainbridge:2004:TDA %D 2004 %O ISBN 0769520855", %V 3 %P 274 %A L. A. Plana W. J. Bainbridge %A S. B. Furber %B Proceedings of ISCA-30 %T Dynamically\0Managing\0the\0Communication-Parallelism\0Trade-Off\0in\0Future\0Clustered\0Processors %L Balasubramonian:2003:DMT %D 2003", %P 275-286 %A R. Balasubramonian %A S. Dwarkadas %A D. H. Albonesi %B 11th\0International\0Symposium\0on\0High-Performance\0Computer\0Architecture\0(HPCA-11)", %T Microarchitectural\0Wire\0Management\0for\0Performance\0and\0Power\0in\0Partitioned\0Architectures %L Balasubramonian:2005:MWM %D 2005 %A R. Balasubramonian %A N. Muralimanohar %A K. Ramani %A V. Venkatachalapathy %J IEEE Micro %T Leveraging\0Wire\0Properties\0at\0the\0Microarchitecture\0Level %L Balasubramonian:2006:LWP %D 2006", %V 26(6) %P %A R. Balasubramonian %A N. Muralimanohar %A K. Ramani %A L. Cheng %A J. Carter %B Proceedings of the 20th\0ACM International Conference on Supercomputing (ICS) %T Design Tradeoffs for Tiled CMP On-Chip Networks %L Balfour:2006:DTF %D 2006 %A James Balfour %A William J. Dally %B Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) %T Arbitrate-and-Move Primitives for High Throughput On-Chip Interconnection Networks %L Balkan:2004:AMP %D 2004 %C Vancouver %V II %P 441-444 %A Aydin O. Balkan %A Gang Qu %A Uzi Vishkin %B Proceedings of the Application-Specific Systems, Architectures and Processors (ASAP) %T A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing %L Balkan:2006:MOT %D 2006 %P 73-80", %A Aydin O. Balkan %A Gang Qu %A Uzi Vishkin %B Proc. IEEE Symp. on High Performance Interconnection Networks (Hot Interconnects) %T Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing %L Balkan:2007:LAD %D 2007 %C Stanford University, CA %A Aydin O. Balkan %A Michael N. Horak %A Gang Qu %A Uzi Vishkin %B Proc. of the Design, Automation and Test in Europe Conference (DATE) %T A Power and Performance Model for Network-on-Chip Architectures %L Banerjee:2004:APA %D 2004 %A Nilanjan Banerjee %A Praveen Vellanki %A Karam S. Chatha %B nocs %T A Power and Energy Exploration of Network-on-Chip Architectures %L Banerjee:2007:PEE %D 2007", %A Arnab Banerjee %A Robert Mullins %A Simon Moore %B Proc. Intl. Symp. on System-on-Chip %T Highly scalable network on chip for reconfigurable systems %L Bartic:2003:HSN %D 2003 %P 79-82 %A T. A. Bartic %A J.-Y. Mignolet %A V. Nollet %A T. Marescaux %A D. Verkest %A S. Vernalde %A R. Lauwereins %N 4 %J IEE Proceedings - Computers and Digital Techniques %T Topology adaptive network-on-chip design and implementation %L Bartic:2005:TAN %D 2005 %V 152 %P 467-472 %A T. A. Bartic %A J.-Y. Mignolet %A V. Nollet %A T. Marescaux %A D. Verkest %A S. Vernalde %A R. Lauwereins %B Field Programmable Logic and Application %T Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation %L Bartic:2006:NOC %D 2004 %S Lecture Notes in Computer Science %I Springer Berlin / Heidelberg %V 3203/2004 %P 637-647 %A T. A. Bartic %A D. Desmet %A J-Y. Mignolet %A T. Marescaux %A D. Verkest %A S. Vernalde %A R. Lauwereins %A J. Miller %A F. Robert %B Proceedings\0of\0the\011th\0IEEE\0International\0Symposium\0on\0Asynchronous\0Circuits\0and\0Systems %T An\0Asynchronous\0NOC\0Architecture\0Providing\0Low\0Latency\0Service\0and\0its\0Multi-Level\0Design\0Framework %L Beigne:2005:AAN %D 2005 %A Edith Beigne %A Fabien Clermidy %A Pascal Vivet %A Alain Clouard %A Marc Renaudin" %B 12th IEEE Intl. Symp. on Asynchronous Circuits and Systems (ASYNC'06) %T Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture %L Beigne:2006:DOO %D 2006 %P 172-183 %A E. Beigne\*' %A P. Vivet %B Proc. 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD) %T Off-line Testing of Delay Faults in NoC Interconnects %L Bengtsson:2006:OLT %D 2006", %A Tomas Bengtsson %A Artur Jutman %A Shashi Kumar %A Zebo Peng %A Raimund Ubar %B IEEE International Symposium on Circuits and Systems %T Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding %L Bertozzi:2002:EEA %D 2002 %P 93-96 %A D. Bertozzi %A L. Benini %A B. Ricco %B Proceedings Design, Automation and Test in Europe Conference and Exhibition %T Low power error resilient encoding for on-chip data buses %L Bertozzi:2002:LPE %D 2002 %P 102-109 %A D. Bertozzi %A L. Benini %A G. De Micheli %T Xpipes:\0A\0Network-on-Chip\0Architecture\0for\0Gigascale\0Systems-on-Chip %J IEEE\0Circuits\0and\0Systems\0Magazine %L Bertozzi:2004:XAN %D 2004 %V 4", %A Davide Bertozzi %A Luca Benini %N 6 %T Error Control Schemes for On-chip Communication Links: the energy-reliability trade-off %J IEEE Transactions on CAD %L Bertozzi:2005:ECS %D 2005", %V 24 %P 818-831 %A D. Bertozzi %A L. Benini %A G. De Micheli %N 2 %T NoC Synthesis Flow for Customized Domain Specific Mutliprocessor Systems-on-Chip %J IEEE Transactions on Parallel and Distributed Systems %L Bertozzi:2005:NSF %D 2005", %V 16 %P 113-129 %A D. Bertozzi %A A. Jalabert %A S. Murali %A R. Tamhankar %A S. Stergiou %A L. Benini %A G. De Micheli %B Proc. of VLSI Design %T Interfacing Cores with On-chip Packet-Switched Networks %L Bhojwani:2003:ICW %D 2003 %A P. Bhojwani %A R. Mahapatra %T Mapping multimode system communication to a network-on-a-chip (NoC) %L Bhojwani:2003:MMS %D 2003", %I Computer Science Department, Texas A&M University, College Station, TX %A Praveen Bhojwani %B Proc. of VLSI Design %T A Heuristic for Peak Power Constrained Design of Network-on-Chip\0(NoC) based Multimode System %L Bhojwani:2005:AHF %D 2005 %A P. Bhojwani %A R. Mahapatra %A E. J. Kim %A T. Chen %B Proc. of Int. Symp. on Quality Electronic Design (ISQED) %T Core Network Interface Architecture and Latency Constrained On-Chip Communication %L Bhojwani:2006:CNI %D 2006", %A P. Bhojwani %A R. Mahapatra %B Proc. of Workshop for Unique Chips and Systems (UCAS-2) %T Forward error correction for on-chip networks %L Bhojwani:2006:FEC %D 2006 %A P. Bhojwani %A R. Singhal %A G. Choi %A R. Mahapatra %B Proc. of Int. Symp. on Quality Electronic Design (ISQED) %T An Infrastructure-IP for online testing of network-on-chip based SoCs %L Bhojwani:2007:AII %D 2007 %P 867-872", %A P. Bhojwani %A R. Mahapatra %B Proc. of ACM/IEEE Design Automation Conference (DAC) %T A Robust Protocol for Concurrent\0On-Line\0Test (COLT) of NoC-based Systems-on-a-Chip %L Bhojwani:2007:ARP %D 2007", %A P. Bhojwani %A R. Mahapatra %B Proceedings of the Fourteenth International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS2004 %T A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling %L Bjerregaard:2004:ACL %D 2004 %P 301-310", %A Tobias Bjerregaard %A Shankar Mahadevan %A Jens Sparso %B Proceedings of the IEEE Norchip Conference (NORCHIP\02004)", %T Virtual Channel Designs for Guaranteeing Bandwidth in Asynchronous Network-on-Chip %L Bjerregaard:2004:VCD %D 2004 %I IEEE %A Tobias Bjerregaard %A Jens Sparso %B Proceedings of International Symposium on System-on-Chip 2005", %T An OCP compliant Network Adapter for GALS-based SoC design using the MANGO Network-on-Chip. %L Bjerregaard:2005:AOC %D 2005 %I IEEE %A Tobias Bjerregaard %A Shankar Mahadevan %A Rasmus Grondahl Olsen %A Jens Sparso %B Proceedings of Design, Automation and Testing in Europe Conference 2005 (DATE05)", %T A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip %L Bjerregaard:2005:ARA %D 2005 %I IEEE %A Tobias Bjerregaard %A Jens Sparso %B Proceedings\0of\0the\011th\0IEEE\0International\0Symposium\0on\0Asynchronous\0Circuits\0and\0Systems", %T A\0Scheduling\0Discipline\0for\0Latency\0and\0Bandwidth\0Guarantees\0in\0Asynchronous\0Network-on-chip %L Bjerregaard:2005:ASD %D 2005 %A Tobias Bjerregaard %A Jens Sparso %T The MANGO clockless network-on-chip: Concepts and implementation %L Bjerregaard:2005:TMC %D 2005 %C Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby %I Informatics and Mathematical Modelling, Technical University of Denmark, DTU %A Tobias Bjerregaard %N 1 %J ACM Computing Surveys %T A survey of research and practices of Network-on-chip %L Bjerregaard:2006:ASO %D 2006 %V 38 %A Tobias Bjerregaard %A Shankar Mahadevan %B Proc.\0of\0the\011th\0IEEE\0Intl.\0Conf.\0on\0Electronics,\0Circuits\0and\0Systems\0(ICECS) %T Automatic\0hardware-efficient\0SoC\0integration\0by\0QoS\0network\0on\0chip %L Bolotin:2004:AHE %D 2004 %A E. Bolotin %A A. Morgenshtein %A I. Cidon %A R. Ginosar %A A. Kolodny" %P 483-486 %J Integration-The VLSI Journal, Special issue: Networks on chip and reconfigurable fabrics %T Cost Considerations in Network on Chip %L Bolotin:2004:CCI %D 2004", %V 38, Issue 1 %P 19-42 %A E. Bolotin %A I. Cidon %A R. Ginosar %A A. Kolodny %J Journal of Systems Architecture, special issue on Network on Chip %T QNoC:\0QoS Architecture and Design Process for Network on Chip %L Bolotin:2004:QQA %D 2004", %V 50 %P 105-128 %A E. Bolotin %A I. Cidon %A R. Ginosar %A A. Kolodny %B nocs %T The Power of Priority: NoC based Distributed Cache Coherency %L Bolotin:2007:PPN %D 2007", %A Evgeny Bolotin %A Zvika Guz %A Israel Cidon %A Ran Ginosar %A Avinoam Kolodny %B In Proc. Design, Automation and Test in Europe (DATE) %T Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh %L Bononi:2006:SAA %D 2006", %A L Bononi %A N Concer %B nocs %T A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study %L Borrione:2007:GMF %D 2007", %A \0Amr\0Helmy Laurence Pierre Dominique\0Borrione %A Julien Schmaltz %B nocs %T A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing %L Bourduas:2007:HRM %D 2007", %A Stephan Bourduas %A Zeljlko Zilic %B 16th IEEE International Workshop on Rapid System Prototyping (RSP'05) %T Heterogeneous\0Modelling\0of\0an\0Optical\0Network-on-Chip\0with\0SystemC %L Briere:2005:HMO %D 2005 %P 10-16 %A Matthieu Brie\*'re %A Emmanuel Drouard %A Fabien Mieyeville %A David Navarro %A Ian O'Connor Fre\*'de\*'ric Gaffiot %B In Proc. of the 15th Annual IEEE International ASIC/SOC Conference %T On-Chip\0Interconnects\0for\0Next\0Generation\0System-on-Chips %L Brinkmann:2002:OCI %D 2002", %A A. Brinkmann %A J.-C. Niemann %A I. Hehemann %A D. Langen %A M. Porrmann andU. Ruckert %B Proceedings\0of\0the\06th\0International\0Symposium\0on\0Advanced\0Research\0in\0Asynchronous\0Circuits\0and\0Systems\0(ASYNC) %T Priority Arbiters %L Bystrov:2000:PA %D 2000", %A A. Bystrov %A D. J. Kinniment %A A. Yakolev %B In Proc. Design, Automation and Test in Europe (DATE) %T GALS networks on chip: new solutions for asynchronous delay-insensitive links %L Campobello:2006:GNO %D 2006", %A G Campobello %A M Castano %A C Ciofi %A D Mangano %B Proc.\0of\019th\0International\0Conference\0on\0VLSI\0Design\0held\0jointly\0with\05th\0International\0Conference\0on\0Embedded\0Systems\0Design\0(VLSID'06) %T A\03Gb/s/wire\0Global\0On-Chip\0Bus\0with\0Near\0Velocity-of-Light\0Latency %L Caputa:2006:A3G %D 2006 %P 117-122 %A Peter Caputa %A Christer Svensson %N 5 %J IEEE Micro, Special Issue on Systems on Chip %T Coping with Latency in SoC Design %L Carloni:2002:CWL %D 2002 %V 22 %P 12 %A L. P. Carloni %A A. L. Sangiovanni-Vincentelli %N TR. no. 562 %T Design and Evaluation of two Asynchronous Token Ring Adapters %L Carrion:1996:DET %D 1996 %I Department of Computing Science, University of Newcastle upon Tyne %A C. Carrion %A A. Yakovlev %T A Validation and Performance Evaluation Tool for ProtoNoc %L Castells:2006:AVP %D 2006", %A David Castells-Rufas %A Jaume Joven %A Jordi Carrabina %B Proc. of the Intl. Conf. on Computer-Aided Design (ICCAD) %T NoCEE: Energy Macro-Model Extraction Methodology for Network on Chip Routers %L Chan:2005:NEM %D 2005 %A Jeremy Chan %A Sri Parameswaran %N 4 %J Proceedings of the IEEE %T RF/wireless interconnect for inter- and intra-chip communications %L Chang:2001:RWI %D 2001 %V 89 %P 456-466", %A M. F. Chang %A V. P. Roychowdhury %A Liyang Zhang %A Hyunchol Shin; Yongxi Qian %N 5", %J IEEE\0Journal\0of\0Solid-State\0Circuits %T Near\0Speed-of-Light\0Signaling\0Over\0On-Chip\0Electrical\0Interconnects %L Chang:2003:NSO %D 2003 %V 38 %P 834-838 %A R. Chang %A N. Talwalkar %A C. Yue %A S. Wong %N 7 %J IEEE Trans. on Electron Devices %T Advanced\0RF/baseband interconnect schemes for inter- and intra-ULSI communications %L Chang:2005:ARB %D 2005 %V 52 %P 1271-1285 %A M.-C. F. Chang %A I. Verbauwhede %A C. Chien %A Zhiwei Xu Jongsun Kim %A J. Ko %A Qun Gu %A Bo-Cheng Lai %B Proceedings of International Conference on Computer Design %T Physical\0Planning\0of\0On-Chip\0Interconnect\0Architectures %L Chen:2002:PPO %D 2002", %P 30-35 %A H. Chen %A B. Yao %A F. Zhou %A C. Cheng. %B Proc. of the 33rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL) %T Compiler-directed channel allocation for saving power in on-chip networks %L Chen:2006:CDC %D 2006 %C New York, NY, USA", %I ACM Press %P 194-205 %A Guangyu Chen %A Feihui Li %A Mahmut Kandemir %B nocs %T A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs %L Chen:2007:LLL %D 2007", %A Shuming Chen %A Xiangyuan Liu %B Proceedings of the 6th Workshop on Complexity-Effective Design, held in conjunction with ISCA-32 %T Wire\0Management\0for\0Coherence\0Traffic\0in\0Chip\0Multiprocessors %L Cheng:2005:WMF %D 2005", %P %A L. Cheng %A N. Muralimanohar %A K. Ramani %A R. Balasubramonian %A J. Carter %B Proceedings of 33rd International Symposium on Computer Architecture (ISCA-33) %T Interconnect-Aware\0Coherence\0Protocols\0for\0Chip\0Multiprocessors %L Cheng:2006:ICP %D 2006", %P 339-350 %A L. Cheng %A N. Muralimanohar %A K. Ramani %A R. Balasubramonian %A J. Carter %B Computer Design, 2008. ICCD 2008. IEEE International Conference on %T Contention-aware application mapping for Network-on-Chip communication architectures %L Chou:2008:CAM %D 2008 %K integer programming, linear programming, network-on-chipcontention-aware application mapping, integer linear programming, mapping heuristic, network-on-chip communication architectures, packet latency %P 164-169 %A Chen-Ling Chou %A R. Marculescu %N 10 %J Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on %T Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels %L Chou:2008:EAP %D 2008 %K multiprocessor interconnection networks, network-on-chiparbitrary allocation scheme, interprocessor communication overhead, multiple voltage levels, multiprocessor interconnection, multiprocessor systems-on-chip, networks on chip, performance-aware incremental mapping, targets real-time applications %V 27 %P 1866-1879 %A Chen-Ling Chou %A U. Y. Ogras %A R. Marculescu %B Proceedings of High-Level Design Validation and Test Workshop (HLDVT) %T An Event-Based Network-On-Chip Monitoring Service %L Ciordas:2004:AEB %D 2004 %P 149-154 %A Calin Ciordas %A \0Twan Basten %A Andrei R\uadulescu %A Kees Goossens %A Jef van Meerbergen %N 4 %J ACM Transactions on Design Automation of Electronic Systems %T An Event-Based Network-on-Chip Monitoring Service %L Ciordas:2005:AEB %D 2005 %O HLDVT'04 Special Issue on Validation of Large Systems", %V 10 %P 702-723 %A Calin Ciordas %A Twan Basten %A Andrei R\uadulescu %A Kees Goossens %A Jef van Meerbergen %B Proc. Int'l Symposium on Circuits and Systems (ISCAS) %T NoC Monitoring: Impact on the Design Flow %L Ciordas:2006:NMI %D 2006", %A Calin Ciordas %A Kees Goossens %A Andrei R\uadulescu %A Kees Goossens %A Twan Basten %I Computer Laboratory, University of Cambridge %T An On-Chip Network Bibliography %L cl-noc-bib %D 2007 %A Robert D. Mullins %B nocs %T Statistical Approach to NoC Design %L Cohen:2008:SAN %D 2008 %A Itamar Cohen %A Ori Rottenstreich %A Isaac Keslassy %B Proc. of the IEEE Intl. Test Conference %T Test scheduling for network-on-chip with BIST and precedence constraints %L Cota:2004:TSF %D 2004 %P 1369-1378 %A Chunsheng Liu Cota %A H Sharif %A Dhiraj Pradhan %B nocs %T NoC Communication Strategies using Time-to-Digital Conversion %L Dalessandro:2007:NCS %D 2007", %A Crescenzo D'Alessandro %A Nikolaos Minas %A Keith Heron %A David Kinniment %A Alex Yakovlev %B Proceedings\0of\0the\0Stanford\0Conference\0on\0Advanced\0Research\0in\0VLSI %T Wire-Efficient\0VLSI\0Multiprocessor\0Communication\0Networks %L Dally:1987:WEV %D 1987 %I MIT Press %E Paul Losleben", %A W. J. Dally %B Proc. of the 17th Annual International Symposium on Computer Architecture (ISCA) %T Virtual-Channel\0Flow\0Control %L Dally:1990:VCF %D 1990 %C Seattle, Washington %P 60-68 %A William J. Dally %B Proc.\0of\0the\038th\0Design\0Automation\0Conference\0(DAC) %T Route\0Packets,\0Not\0Wires:\0On-Chip\0Interconnection\0Networks %L Dally:2001:RPN %D 2001 %A William J. Dally %A Brian Towles %T Principles\0and\0Practices\0of\0Interconnection\0Networks %L Dally:2003:PAP %D 2003", %I Morgan Kaufmann %A William J. Dally %A Brian Towles %B IP-Based\0SOC\0Design %T Concepts and Implementation of the Philips Network-on-Chip %L Dielissen:2003:CAI %D 2003 %A John Dielissen %A Andrei R\uadulescu %A Kees Goossens %A Edwin Rijpkema %B nocs %T NOC-centric security of reconfigurable SoC %L Diguet:2007:NCS %D 2007", %A Jean-Philippe Diguet %A Guy Gogniat %A Samuel Evain %A Romain Vaslin %A Emmanuel Juin %B Proceedings\0of\0ASYNC'05 %T An Asynchronous Router for Multiple Service Levels Networks on Chip %L Dobkin:2005:AAR %D 2005 %A R. Dobkin %A V. Vishnyakov %A E. Friedman %A R. Ginosar" %P 44-53 %B Proc.\0Design\0Automation\0and\0Test\0in\0Europe\0(DATE) %T On-Chip\0Stochastic\0Communication %L Dumitras:2003:OCS %D 2003 %A Tudor Dumitras %A Radu Marculescu %B Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC) %T Towards on-chip fault-tolerant communication %L Dumitras:2003:TOC %D 2003", %A T. Dumitras %A S. Kerner %A R. Marculescu %B In Proc. Design, Automation and Test in Europe (DATE) %T Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application %L Dumitrascu:2006:FMP %D 2006", %A F Dumitrascu %A I Bacivarov %A L Pieralisi %A M Bonaciu %A A Jerraya %B Proceedings of CASES %T High-level power analysis for on-chip networks %L Eisley:2004:HLP %D 2004 %I ACM Press", %P 104-115 %A Noel Eisley %A Li-Shiuan Peh %B Proc. of the 39th Annual Intl. Symp. on Microarchitecture (MICRO) %T In-Network Cache Coherence %L Eisley:2006:INC %D 2006", %A Noel Eisley %A Li-Shiuan Peh %A Li-Shang %T Network on Chip: PANACEA - A Nostrum Integration %L Elguindi:2005:NOC %L Nostrum %D 2005 %I Swiss Federal Institute of Technology Zurich %A Nadim El Guindi %A Pascal Elsener %B IEEE International ASIC/SOC Conference %T An Analytical Power Estimation Model For Crossbar Interconnects %L Essakimuthu:2002:AAP %D 2002 %A G. Essakimuthu %A N. Vijaykrishnan %A M. J. Irwin %B Proc.\0of\0the\0second\0ACiD-WG\0Workshop %T The\0Distributed\0Clock\0Generator %L Fairbanks:2002:TDC %D 2002 %C Munich,\0Germany %A Scott Fairbanks %A Simon Moore %B Proceedings\0of\0the\011th\0International\0Symposium\0on\0Asynchronous\0Circuits\0and\0Systems %T Self-timed Circuitry for Global Clocking %L Fairbanks:2005:STC %D 2005", %A Scott Fairbanks %A Simon Moore %B Proceedings of the 15th International Conference on Microelectronics (ICM'03), Cairo, Egypt %T An Asynchronous Low Latency Arbiter for Quality of Service (QoS) Applications %L Felicijan:2003:AAL %D 2003 %O ISBN 9770520101", %P 123-126 %A W. J. Bainbridge T. Felicijan %A S. B. Furber %J IEEE Transactions on Very Large Scale Integration (VLSI) Systems %T An Asynchronous Ternary Logic Signaling System %L Felicijan:2003:AAT %D 2003", %V 11(6) %P 1114-1119 %A T. Felicijan %A S. B. Furber %B Proceedings IEEE International SOC Conference %T An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support %L Felicijan:2004:AAO %D 2004 %O ISBN 0780384458", %P 274-277 %A T. Felicijan %A S. B. Furber %B nocs %T Region-Based Routing. An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips %L Flich:2007:RBR %D 2007", %A Jose Flich %A Andres Mejia %A Pedro Lopez %A Jose Duato %N 5 %J IEEE Micro %T A scalable high-performance computing solution for networks on chips %L Forsell:2002:ASH %D 2002 %V 22 %P 46-55 %A M. Forsell %J Proceedings 2005 International Symposium on System-on-Chip %T Future Trends in SoC Interconnect %L Furber:2005:FTI %D 2005 %P 183-186 %A S. B. Furber %A J. Bainbridge %B Proceedings\0of\0Hot\0Interconnects\0Symposium\0IV", %T Scalable\0Pipelined\0Interconnect\0for\0Distributed\0Endpoint\0Routing:\0The\0SGI\0SPIDER\0Chip %L Galles:1996:SPI %D 1996 %A M. Galles %B Dynamic and Robust Streaming In And Between Connected Consumer-Electronics Devices %T Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the \AEthereal Network on Chip %L Gangwal:2005:BPS %D 2005 %S Philips Research Book Series %I Springer %V 3 %E Peter van der Stok %P 1-36 %A Om Prakash Gangwal %A Andrei R\uadulescu %A Kees Goossens %A Santiago Gonz\'alez Pestana %A Edwin Rijpkema %B Electronic Notes in Theoretical Computer Science, 200(1) %T Elastic Flow in an Application Specific Network-on-Chip %L Gebhardt:2008:EFA %D 2008 %I Elsevier", %P 3-15 %A Daniel Gebhardt %A Kenneth S. Stevens %B Proc. Working Conference on Correct Hardware Design and Verification Methods (CHARME) %T Deadlock Prevention in the \AEthereal Protocol %L Gebremichael:2005:DPI %D 2005 %S Lecture Notes in Computer Science (LNCS) %V 3725 %P 345-348 %E Dominique Borrione and Wolfgang Paul %A Biniam Gebremichael %A Frits Vaandrager %A Miaomiao Zhang %A Kees Goossens %A Edwin Rijpkema %A Andrei R\uadulescu %B Proc. of IEEE DATE %T A Complete Network-on-Chip Emulation Framework %L Genko:2005:ACN %D 2005 %P 246-251", %A N. Genko %A D. Atienza %A G. De Micheli %A others %B ISCAS 2005 %T A Novel Approach for Network on Chip Emulation %L Genko:2005:ANA %D 2005", %C Kobe, Japan %P 2365-2368 %A N. Genko %A D. Atienza %A G. De Micheli %A L. Benini %A J. M. Mendias %A R. Hermida %A F. Catthoor %B Proc. of ParCo %T NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration %L Genko:2005:NEO %D 2005", %A N. Genko %A D. Atienza %A G. De Micheli %A others %B nocs %T NoC-Based FPGA: Architecture and Routing %L Gindin:2007:NFA %D 2007", %A Roman Gindin %A Israel Cidon %A Idit Keidar %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T Cost-Performance Trade-offs in Networks on Chip: A Simulation-Based Approach %L Gonzalez:2004:CPT %D 2004 %P 764-769 %A Santiago Gonz\'alez Pestana %A Edwin Rijpkema %A Andrei R\uadulescu %A Kees Goossens %A Om Prakash Gangwal %B International Symposium on Circuits and Systems %I IEEE Circuits and Systems Society", %T A Protocol And Memory Manager For On-Chip Communication %L Goossens:2001:APA %D 2001 %C Sydney %V II %P 225-228 %A K. G. W. Goossens %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T Networks on Silicon: Combining Best-Effort and Guaranteed Services %L Goossens:2002:NOS %D 2002 %P 423-425 %A K. Goossens %A J. van Meerbergen %A A. Peeters %A P. Wielage %B Coordination languages and models %N 2315 %T The Cost of Communication Protocols and Coordination Languages in Embedded Systems %L Goossens:2002:TCO %D 2002 %S Lecture notes in computer science %I Springer Verlag", %E Farhad Arbab and Carolyn Talcott %P 174-190 %A K. G. W. Goossens %A O. P. Gangwal %B Networks on Chip %T Guaranteeing The Quality of Services in Networks on Chip %L Goossens:2003:GTQ %D 2003 %I Kluwer %P 61-82 %E Axel Jantsch and Hannu Tenhunen %A Kees Goossens %A John Dielissen %A Jef van Meerbergen %A Peter Poplavko %A Andrei R\uadulescu %A Edwin Rijpkema %A Erwin Waterlander %A Paul Wielage %B Interconnect-Centric Design for Advanced SoC and NoC %T Interconnect and Memory Organization in SOCs for advanced Set-Top Boxes and TV --- Evolution, Analysis, and Trends %L Goossens:2004:IAM %D 2004 %I Kluwer %E Jari Nurmi, Hannu Tenhunen and Axel Jantsch %P 399-423 %A Kees Goossens %A Om Prakash Gangwal %A Jens Ro\*:ver %A A.\0P. Niranjan %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification %L Goossens:2005:ADF %D 2005 %P 1182-1187 %A Kees Goossens %A John Dielissen %A Om Prakash Gangwal %A Santiago Gonz\'alez Pestana %A Andrei R\uadulescu %A Edwin Rijpkema %B Proc. Int'l Conference on Application of Concurrency to System Design (ACSD) %T Formal Methods for Networks on Chips %L Goossens:2005:FMF %D 2005 %P 188-189 %A Kees Goossens %B Proc. Int'l Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) %T Networks on Chip for Consumer Electronics %L Goossens:2005:NOC %D 2005 %P 227-230 %A Kees Goossens %B Dynamic and Robust Streaming In And Between Connected Consumer-Electronics Devices %T Service-Based Design of Systems on Chip and Networks on Chip %L Goossens:2005:SBD %D 2005 %S Philips Research Book Series %I Springer %V 3 %E Peter van der Stok %P 37-60 %A Kees Goossens %A Santiago Gonz\'alez Pestana %A John Dielissen %A Om Prakash Gangwal %A Jef van Meerbergen %A Andrei R\uadulescu %A Edwin Rijpkema %A Paul Wielage %N 5 %J IEEE Design and Test of Computers %T The \AEthereal Network on Chip: Concepts, Architectures, and Implementations %L Goossens:2005:TAN %D 2005 %V 22 %A Kees Goossens %A John Dielissen %A Andrei R\uadulescu %B nocs %T Transaction-Based Communication-Centric Debug %L Goossens:2007:TBC %D 2007", %A Kees Goossens %A Bart Vermeulen %A Remco van Steeden %A Martijn Bennebroek %B nocs %T Implementation and Evaluation of a Dynamically Routed Processor Operand Network %L Gratz:2007:IED %D 2007", %A Paul Gratz %A Karthikeyan Sankaralingam %A Heather Hanson %A Premkishore Shivakumar %A Robert McDonald %A Stephen Keckler %A Doug Burger %B nocs %T Implications of Rent's Rule for NoC Design and Its Fault-Tolerance %L Greenfield:2007:IRR %D 2007", %A Daniel Greenfield %A Arnab Banerjee %A Jeong-Gun Lee %A Simon Moore %T Design of Frequency Controller for Minimizing Power Consumption In Network-on-Chip %L Guang:2005:DOF %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Liang Guang %B Proc. of DATE %T A generic architecture for on-chip packet-switched interconnections %L Guerrier:2000:AGA %D 2000 %I ACM Press", %P 250-256 %A Pierre Guerrier %A Alain Greiner %B In\0Proc.\0Design,\0Automation\0and\0Test\0in\0Europe\0(DATE) %T Efficient Link Capacity and QoS Design for Network-on-Chip %L Guz:2006:ELC %D 2006 %A Z. Guz %A I. Walter %A E. Bolotin %A I. Cidon %A R. Ginosar %A A. Kolodny" %P 9-14 %B Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) %T A Unified Approach to Constrained Mapping and Routing on Network-on-Chip Architectures %L Hansson:2005:AUA %D 2005 %A Andreas Hansson %A Kees Goossens %A Andrei R\uadulescu %B nocs %T Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases %L Hansson:2007:TCN %D 2007", %A Andreas Hansson %A Kees Goossens %B Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) %T Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip %L Harmanci:2005:QMA %D 2005", %A Mehmet Harmanci %A Nuria Pazos Escudero %A Yusuf Leblebici %A Paolo Ienne %B Proceedings of the IEEE International Conference on Group IV Photonics %T On-chip Optical Interconnect Roadmap: Challenges and Critical Directions %L Haurylau:2005:OCO %D 2005 %P 17-19 %A M. Haurylau %A H. Chen %A J. Zhang %A G. Chen %A N. A. Nelson %A D. H. Albonesi %A E. G. Friedman %A P. M. Fauchet %B Proceeding of the IEEE NorChip Conference %T Network on Chip: An architecture for billion transistor era %L Hemani:2000:NOC %D 2000 %L Nostrum %A Ahmed Hemani %A Axel Jantsch %A Shashi Kumar %A Adam Postula %A Johnny O\*:berg %A Mikael Millberg %A Dan Lindqvist %B 17th International Conference on VLSI Design %T On-chip networks: A scalable, communication-centric embedded system design paradigm. %L Henkel:2004:OCN %D 2004 %P 845- %A Jo\*:rg Henkel %A Wayne Wolf %A Srimat T. Chakradhar %B ISLPED '05: Proc. of the 2005 Intl. Symp. on Low Power Electronics and Design %T Replacing global wires with an on-chip network: a power analysis %L Heo:2005:RGW %D 2005 %C New York, NY, USA", %I ACM Press %P 369-374 %A Seongmoo Heo %A Krste Asanovic\*' %N 4", %J Proceedings of the IEEE %T The Future of Wires %L Ho:2001:TFO %D 2001 %V 89 %P 490-504 %A R. Ho %A K. Mai %A M. Horowitz %B The Ninth International Symposium on High-Performance Computer Architecture (HPCA'03) %T A\0Methodology\0for\0Designing\0Efficient\0On-Chip\0Interconnects\0on\0Well-Behaved\0Communication\0Patterns\0 %L Ho:2003:AMF %D 2003", %P 377 %A Wai Hong Ho %A Timothy Mark Pinkston %B Symposium on VLSI circuits %T Efficient On-Chip Global Interconnects %L Ho:2003:EOG %D 2003", %A Ron Ho %A Ken Mai %A Mark Horowitz %T On-Chip Wires: Scaling and Efficiency %L Ho:2003:OCW %D 2003", %I Stanford University %A Ron Ho %B The\010th\0IEEE\0International\0Symposium\0on\0Asynchronous\0Circuits\0and\0Systems %T Long wires and asynchronous control %L Ho:2004:LWA %D 2004 %A R. Ho %A J. Gainsley %A R. Drost" %B nocs %T Architecture of the Scalable Communications Core %L Hoffman:2007:ASC %D 2007", %A Jeffrey Hoffman %A David Arditti Ilitzky %A Anthony Chun %A Aliaksei Chapyzhenka %B IEEE International Symposium on Circuits and Systems (ISCAS) %T An Area-efficient, Pulse-based Interconnect %L Hollis:2006:AAE %D 2006 %A Simon Hollis %A Simon W. Moore %B Proc. 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD) %T Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions %L Holsmark:2006:DFR %D 2006", %A R. Holsmark %A M. Palesi %A S. Kumar %B Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) %T VLSI architecture based on packet data transfer scheme and its application %L Homma:2005:VAB %D 2005", %A Yuya Homma %A Michitaka Kameyama %A Yoshichika Fujioka %A Nobuhiro Tomabechi %B In Proc. Design, Automation and Test in Europe (DATE) %T A concurrent testing method for NoC switches %L Hosseinabady:2006:ACT %D 2006", %A M Hosseinabady %A A Banaiyan %A M N Bojnordi %A Z Navabi %B Proc. Design Automation Conference. Asia and South Pacific (ASP-DAC) %T Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints %L Hu:2003:EAM %D 2003", %A Radu Marculescu Jingcao Hu %B Proc. Design, Automation and Test in Europe Conference %T Exploiting\0the\0Routing\0Flexibility\0for\0Energy/Performance\0Aware\0Mapping\0of\0Regular\0NoC\0Architectures %L Hu:2003:ETR %D 2003", %A J. Hu %A R. Marculescu. %B Proc. IEEE/ACM Intl. Conf. on Computer Aided Design %T Application ­Specific Buffer Space Allocation for Networks­on­Chip Router Design %L Hu:2004:ASB %D 2004 %C San Jose, CA %A Jingcao Hu %A Radu Marculescu %B Design Automation Conference %T DyAD Smart Routing for Networks- %L Hu:2004:DSR %D 2004 %A Jingcao Hu %A Radu Marculescu %N 4 %J IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems %T Energy- and Performance-Aware Mapping for Regular NoC Architectures %L Hu:2005:EPM %D 2005 %V 24 %A Jingcao Hu %A Radu Marculescu %B Proceedings of the Intl. Conf. on Computer Design (ICCD) %T Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimization %L Hu:2005:PSO %D 2005 %A Yuanfang Hu %A Hongyu Chen %A Yi Zhu %A Andrew A. Chien %A Chung-Kuan Cheng %B Proc. of the Intl. Conf. on Computer Design (ICCD) %T Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture %L Hung:2004:TAI %D 2004 %A W. Hung %A C. Addo-Quaye %A T. Theocharides %A Y. Xie %A N. Vijaykrishnan %A M. J. Irwin %N 5 %T The Network-on-Chip Paradigm in Practice and Research %J Design \& Test of Computers %L Ivanov:2005:TNO %D 2005", %V 22 %P 399-403 %A A. Ivanov %A G. De Micheli %B Design,\0Automation\0and\0Test\0in\0Europe\0(DATE) %T xpipesCompiler:\0A\0tool\0for\0instantiating\0application\0specific\0Networks\0on\0Chip", %L Jalabert:2004:XAT %D 2004 %C Paris,\0France %A Antoine Jalabert %A Srinivasan Murali %A Luca Benini %A Giovanni De Micheli %B Workshop at the European Solid State Circuits Conference %T Networks on Chip %L Jantsch:2001:NOC %D 2001 %L Nostrum %A Axel Jantsch %A Juha-Pekka Soininen %A Martti Forsell %A Li-Rong Zheng %A Shashi Kumar %A Mikael Millberg %A Johnny Öberg %B Proceedings of the Conference Radio vetenskap och Kommunication %T Network on Chip %L Jantsch:2002:NOC %D 2002 %L Nostrum %C Stockholm %A Axel Jantsch %B Proceedings of the Euromicro Symposium on Digital System Design %T NoCs: A new Contract between Hardware and Software %L Jantsch:2003:NAN %D 2003 %L Nostrum %O Invited keynote %A Axel Jantsch %T Networks on Chip %L Jantsch:2003:NOC %D 2003 %L Nostrum %I Kluwer Academic Publishers %E Axel Jantsch and Hannu Tenhunen %B Networks on Chip %T Will Networks on Chip Close the Productivity Gap? %L Jantsch:2003:WNO %D 2003 %L Nostrum %I Kluwer Academic Publishers %E Axel Jantsch and Hannu Tenhunen %P 3-18 %A Axel Jantsch %A Hannu Tenhunen %N 2-3 %J Journal of Systems Architecture %T Special Issue on Networks on Chip - guest editor's introduction %L Jantsch:2004:SIO %D 2004 %L Nostrum %V 50 %A Axel Jantsch %A Johnny O\*:berg %A Hannu Tenhunen %B Proceedings of the IEEE International Symposium on Circuits and Systems %T Power analysis of link level and end-to-end data protection on networks on chip %L Jantsch:2005:PAO %D 2005 %L Nostrum %A Axel Jantsch %A Robert Lauter %A Arseni Vitkowski %B Proceedings of the 2005 International Conference on Parallel Processing (ICPP) %T Peak Power Control for a QoS Capable On-Chip Network %L Jin:2005:PPC %D 2005 %P 585-592 %A Y. Jin %A E. J. Kim %A and K. H. Yum %B Proceedings of the Second Intl. Conf. on Embedded Software and Systems (ICESS) %T Network on Chip for Parallel DSP Architectures %L Jing:2005:NOC %D 2005 %A Yuanli Jing %A Xiaoya Fan %A Deyuan Gao %A Jian Hu %B Conference on Design, Automation and Test in Europe (DATE) %T Interconnect tuning strategies for high-performance ICs %L Kahng:1998:ITS %D 1998 %P 471-478", %A A. B. Kahng %A S. Muddu %A E. Sarto %A R. Sharma %B Proc. of the 37th conference on Design automation (DAC) %T On switch factor based analysis of coupled RC interconnects %L Kahng:2000:OSF %D 2000 %P 79-84", %A Andrew B. Kahng %A Sudhakar Muddu %A Egino Sarto %B Proc. International Symposium on System-on-Chip %T New Adaptive Routing Algorithm for Extended Generalized Fat Trees On-Chip %L Kariniemi:2003:NAR %D 2003 %C Tampere, Finland %P 113-188", %A Heikki Kariniemi %A Jari Nurmi %B Proc. International Conference on Computer Science and Technology %T New Routing Algorithm for Improving the Throughput of Fat Tree Interconnection Networks %L Kariniemi:2003:NRA %D 2003", %C Cancun, Mexico %A Heikki Kariniemi %A Jari Nurmi %B Proc. International Conference on Computer Science and Technology %T Performance Evaluation of Three Arbiters for Internally Buffered Crossbar Switch %L Kariniemi:2003:PEO %D 2003", %C Cancun, Mexico %A Heikki Kariniemi %A Jari Nurmi %N 5-6 %J Computing and Informatics %T Performance Evaluation and Implementation of Two Adaptive Routing Algorithms for XGFT Networks %L Kariniemi:2004:PEA %D 2004 %I Slovak Academic Press", %V 23 %P 415-435 %A Heikki Kariniemi %A Jari Nurmi %B Proc. The 7th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'04) %T Performance Evaluation and Implementation of Two Adaptive Routing Algorithms for XGFT Networks %L Kariniemi:2004:PEI %D 2004", %A Heikki Kariniemi %A Jari Nurmi %B Proc. International Symposium on System-on-Chip SoC2004 %T Reusable XGFT Interconnect IP for Network-On-Chip Implementations %L Kariniemi:2004:RXI %D 2004 %C Tampere, Finland %P 95-102", %A Heikki Kariniemi %A Jari Nurmi %B Proc. International Conference on Field Programmable Logic and Applications %T Fault-Tolerant XGFT Network-on-Chip for Multi-Processor System-on-Chip Circuits %L Kariniemi:2005:FTX %D 2005 %C Tampere, Finland %P 203-210", %A Heikki Kariniemi %A Jari Nurmi %B Proc. The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) %T Versatile Modular Switch Architecture for Improving the QOS of the XGFT Network-on-Chip %L Kariniemi:2005:VMS %D 2005 %C Sopron, Hungary %P 105-112", %A Heikki Kariniemi %A Jari Nurmi %B 4th PROGRESS Symp. on Embedded Systems, Nieuwegein, Netherlands %T A Survey of Efficient On-Chip Communications for SoC %L Kavaldjiev:2003:ASO %D 2003", %I STW Technology Foundation %P 129-140 %A N. K. Kavaldjiev %A G. J. M. Smit %B EUROMICRO Symp. on Digital System Design (DSD), Rennes, France %T An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable System-on-Chip %L Kavaldjiev:2004:AEE %D 2004", %I IEEE Computer Society Press %P 492-498 %A N. K. Kavaldjiev %A G. J. M. Smit %B IEEE Int. SOC Conf., Santa Clara, California %T A Virtual Channel Router for On-chip Networks %L Kavaldjiev:2004:AVC %D 2004", %I IEEE Computer Society Press %P 289-293 %A N. K. Kavaldjiev %A G. J. M. Smit %A P. G. Jansen %B 5th PROGRESS Symp. on Embedded Systems, Nieuwegein, the Netherlands %T Two Architectures for On-chip Virtual Channel Router %L Kavaldjiev:2004:TAF %D 2004", %I STW Technology Foundation %P 90-95 %A N. K. Kavaldjiev %A G. J. M. Smit %A P. G. Jansen %B EUROMICRO Symposium on Digital System Design, Porto, Portugal %T Throughput of Streaming Applications Running on a Multiprocessor Architecture %L Kavaldjiev:2005:TOS %D 2005", %I IEEE Computer Society Press %P 350-355 %A N. K. Kavaldjiev %A G. J. M. Smit %A P. G. Jansen %B Proceedings of REALWAN %T Simulation of Real Home Healthcare Sensor Networks Utilizing IEEE 802.11g Biomedical Network-on-Chip %L Khatib:2005:SOR %D 2005 %L Nostrum %C Stockholm", %A Iyad Al Khatib %A Axel Jantsch %A Mohammad Saleh %B Proceedings of the Infocom 2005 Conference - Student Workshop %T Wireless Network-on-Chips as Autonomous Systems: A Novel Solution for Biomedical Healthcare and Space Exploration Sensor-Networks %L Khatib:2005:WNO %D 2005 %L Nostrum %A Iyad Al Khatib %A Axel Jantsch %A Bassam Kayal %A Rustam Nabiev %A Sven Jonsson %B Proceedings of the ACM Computing Frontiers %T MPSoC ECG Biochip: A Multiprocessor System-on-Chip for Real-Time Human Heart Monitoring and Analysis %L Khatib:2006:MEB %D 2006 %L Nostrum %A Iyad Al Khatib %A Davide Bertozzi %A Francesco Poletti %A Luca Benini %A Axel Jantsch %A Mohamed Bechara %A Hasan Khalifeh %A Mazen Hajjar %A Rustam Nabiev %A Sven Jonsson %B Proc. of the Intl. Symp. on Low power Electronics and Design (ISLPED'03) %T Energy characterization of a tiled architecture processor with on-chip networks %L Kim:2003:ECO %D 2003 %A J. S. Kim %A M. B. Taylor %A J. Miller %A D. Wentzlaff %B International Symposium on Low Power Electronics and Design (ISLPED'03) %T Energy\0Optimization\0Techniques\0in\0Cluster\0Interconnects %L Kim:2003:EOT %D 2003", %A E. J. Kim %A K. H. Yum %A G. M. Link %A C. R. Das %A N. Vijaykrishnan %A Mahmut Kandemir %A Mary Jane Irwin %B Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) %T An Arbitration Look-Ahead Scheme for Reducing End-to-End Latency in Networks-on-Chip %L Kim:2005:AAL %D 2005", %A Kwanho Kim %A Se-Joong Lee %A Kangmin Lee %A Hoi-Jun Yoo %B Proc. Intl. SoC Design Conference %T Asynchronous FIFO Interfaces for GALS On-Chip Switched Networks %L Kim:2005:AFI %D 2005 %P 186-189 %A Daewook Kim %A Manho Kim %A Gerald E. Sobelman %B Proceedings\0of\0the\042nd\0Design\0Automation\0Conference\0(DAC) %T A Low Latency Router Supporting Adaptivity for On-Chip Interconnects %L Kim:2005:ALL %D 2005", %A J. Kim %A D. Park %A T. Theochar %A N. Vijaykrishnan %A C. R. Das %B Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) %T A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip %L Kim:2005:ARC %D 2005", %A Donghyun Kim %A Kangmin Lee %A Se-Joong Lee %A Hoi-Jun Yoo %B First Symposium on Architectures for Networking and Communication Systems. %T Design and Analysis of an NoC Architecture from Performance, Reliability and Energy Perspective %L Kim:2005:DAA %D 2005 %A J. Kim %A D. Park %A C. Nicopoulus %A N. Vijaykrishnan %A C. Das. %B Proc. of the 33st Annual Intl. Symp. on Computer Architecture (ISCA) %T A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks %L Kim:2006:AGD %D 2006 %A Jongman Kim %A C. Nicopoulos %A Dongkook Park %B nocs %T Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC %L Kim:2007:SRC %D 2007", %A Donghyun Kim %A Kwanho Kim %A Joo-Young Kim %A Seung-Jin Lee %A Hoi-Jun Yoo %B nocs %T ASC, a SystemC extension for Modeling Asynchronous Systems, and its application to an Asynchronous NoC %L KochHofer:2007:ASC %D 2007", %A Cedric Koch-Hofer %A Marc Renaudin %A Vvain Thonnart %A Pascal Vivet %B 31st\0International\0Symposium\0on\0Computer\0Architecture\0(ISCA-31) %T The\0Vector-Thread\0Architecture %L Krashinsky:2004:TVT %D 2004 %C Munich,\0Germany", %A Ronny Krashinsky %A Christopher Batten %A Mark Hampton %A Steve Gerding %A Brian Pharris %A Jared Casper %A Krste Asanovic %B Proceedings of IEEE Computer Society Annual Symposium on VLSI %T A Network on Chip Architecture and Design Methodology %L Kumar:2002:ANO %D 2002 %L Nostrum %A Shashi Kumar %A Axel Jantsch %A Juha-Pekka Soininen %A Martti Forsell %A Mikael Millberg %A Johnny O\*:berg %A Kari Tiensyrj\"a %A Ahmed Hemani %B Networks on Chip %T On Packet Switched Networks for On-chip Communication %L Kumar:2003:OPS %D 2003 %L Nostrum %I Kluwer Academic Publishers %E Axel Jantsch and Hannu Tenhunen %P 85-106 %A Shashi Kumar %B Proc. of the 34th Intl. Symp. on Computer Architecture (ISCA-34)", %T Express virtual-channels: towards the ideal interconnection fabric %L Kumar:2007:EVC %D 2007 %A Amit Kumar %A Li-Shiuan Peh %A Partha Kundu %A Niraj K. Jha %B Thirty-Fifth Asilomar Conference on Signals, Systems, and Computers %T Adaptive System on a Chip (aSoC) for Low-Power Signal Processing %L Laffely:2001:ASO %D 2001 %A Andrew Laffely %A Jian Liang %A Prashant Jain %A Ning Weng %A Wayne Burleson %A Russell Tessier %B Proc.\0of\0the\0IEEE\0Conference\0on\0Image\0Processing %T Adaptive System on a Chip: A Backbone for Power-Aware Signal Processing Cores %L Laffely:2003:ASO %D 2003 %C Barcelona, Spain %A A. Laffely %A J. Liang %A R. Tessier %A W. Burleson %T Breaking the synchronous barrier for Systems-on-Chip communication and synchronization %L Lavagno:2004:BTS %D 2004 %A L. Lavagno %A S. W. Moore" %B Proc. ACM/IEEE Design Automation Conf. %T Design Space Exploration and Prototyping for On-chip Multimedia Applications %L Lee:2006:DSE %D 2006 %C San Francisco %A Hyung Gyu Lee %A Umit Y. Ogras %A Radu Marculescu %A Naehyuck Chang %N 2 %J IEEE Transactions on VLSI Systems %T Low-Power Network-on-Chip for High-Performance SoC Design %L Lee:2006:LNF %D 2006 %V 14 %A Kangmin Lee %A Se-Joong Lee %A Hoi-Jun Yoo %N 3 %J ACM Trans. on Design Automation of Electronic Systems (TODAES) %T On-chip Communication Architecture Exploration: A Quantitative Evaluation of Point-to-Point, Bus, and Network-on-Chip Approaches %L Lee:2007:OCA %D 2007", %V 12 %A Hyung Gyu Lee %A Naehyuck Chang %A Umit Y. Ogras %A Radu Marculescu %T Estimation of Power Consumption in Wormhole Routed Networks on Chip %L Li:2005:EOP %L Nostrum %D 2005 %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %A Tong Li %B IEEE Computer Society Annual Symposium on VLSI %T Exploiting Software Pipelining for Network-on-Chip architectures %L Li:2006:ESP %D 2006 %A F. Li %A M. Kandemir %A I. Kolcu %B the IEEE International Conference on Parallel Architectures and Compilation Techniques %T aSOC:\0A\0Scalable,\0Single-Chip\0Communications\0Architecture %L Liang:2000:AAS %D 2000", %P 524-529 %A Jian Liang %A S. Swaminathan %A R. Tessier %B Proceedings\0of\0the\011th\0Symposium\0on\0High\0Performance\0Interconnects", %T Nexus:\0An\0Asynchronous\0Crossbar\0Interconnect\0for\0Synchronous\0System-on-Chip\0Designs %L Lines:2003:NAA %D 2003 %A Andrew Lines %T Improving the Performance of a Wormhole Router and Wormhole Flow Control %L Liu:2005:ITP %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Ming Liu %B Design, Automation and Test in Europe Conference and Exhibition %T Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip %L Liu:2006:RBT %D 2006 %I DATE 2006 %A C. Liu %A Z. Link %A Dhiraj Pradhan %B Networks on Chip %T NoC Application Programming Interfaces %L Lu:2003:NAP %D 2003 %L Nostrum %I Kluwer Academic Publishers %E Axel Jantsch and Hannu Tenhunen %P 239-260 %A Zhonghai Lu %A Raimo Haukilahti %N TRITA-IMIT-LECS R 03:02, version 1.0 %T Network-on-Chip Assembler Language %L Lu:2003:NOC %D 2003 %L Nostrum %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %C Stockholm, Sweden %A Zhonghai Lu %A Axel Jantsch %B Proceedings of the International Symposium on System-on-Chip 2003 %T Flit Admission in On-chip Wormhole-switched Networks with Virtual Channels %L Lu:2004:FAI %D 2004 %L Nostrum %A Zhonghai Lu %A Axel Jantsch %B Proceedings of the IEEE NorChip Conference %T Flit Ejection in On-chip Wormhole-switched Networks with Virtual Channels %L Lu:2004:FEI %D 2004 %L Nostrum %A Zhonghai Lu %A Axel Jantsch %B Proceedings of the 9th World Multi-Conference on Systemics, Cybernetics and Informatics %T A power efficient flit-admission scheme for wormhole-switched networks on chip %L Lu:2005:APE %D 2005 %L Nostrum %A Zhonghai Lu %A Li Tong %A Bei Yin %A Axel Jantsch %I Royal Institute of Technology %T A User Introduction to NNSE: Nostrum Network-on-Chip Simulation Environment %L Lu:2005:AUI %D 2005 %L Nostrum, NNSE %C Stockholm %A Zhonghai Lu %B Proceedings of the Asian Pacific Design Automation Conference %T Feasibility Analysis of Messages for On-chip Networks Using Wormhole Routing %L Lu:2005:FAO %D 2005 %L Nostrum %A Zhonghai Lu %A Axel Jantsch %A Ingo Sander %B Swedish System-on-Chip Conference (SSoCC'03) %T NNSE: Nostrum Network-on-Chip Simulation Environment %L Lu:2005:NNN %D 2005 %L Nostrum, NNSE %A Zhonghai Lu %A Rikard Thid %A Mikael Millberg %A Erland Nilsson %A Axel Jantsch %B Proceedings of the Forum on Design Languages %T Refinement of A Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication %L Lu:2005:ROA %D 2005 %L Nostrum %A Zhonghai Lu %A Ingo Sander %A Axel Jantsch %B Proceedings of the 5th International Workshop on Systems on Chip (IWSOC) %T Traffic Configuration for Evaluating Networks on Chips %L Lu:2005:TCF %D 2005 %L Nostrum, NNSE %A Zhonghai Lu %A Axel Jantsch %B Proceedings of the IEEE Computer Society Annual Symposium on VLSI %T Connection-oriented Multicasting in Wormhole-switched Networks on Chip %L Lu:2006:COM %D 2006 %L Nostrum %A Zhonghai Lu %A Bei Yin %A Axel Jantsch %B Proceedings of GLSVLSI %T Evaluation of Onchip Networks Using Deflection Routing %L Lu:2006:EOO %D 2006 %L Nostrum %A Zhonghai Lu %A Mingchen Zhong %A Axel Jantsch %B Advances in Design and Specification Languages for SoCs - Selected Contributions from FDL\02005 %T Refining Synchronous Communication onto Network-on-Chip Best-effort Services %L Lu:2006:RSC %D 2006 %L Nostrum %I Springer Verlag %E Alain Vachoux %A Zhonghai Lu %A Ingo Sander %A Axel Jantsch %B Proceedings of Design, Automation and Testing in Europe Conference 2005 (DATE05)", %T A Network Traffic Generator Model for Fast Network-on-chip Simulation %L Mahadevan:2005:ANT %D 2005 %I IEEE %A Shankar Mahadevan %A Federico Angiolini %A Michael Storgaard %A Ramus Grondahl Olsen %A Jens Sparso %A Jan Madsen %B nocs %T A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing %L Mak:2007:HAD %D 2007", %A Terrence S. T. Mak %A Pete Sedcole %A Peter Y. K. Cheung %A Wayne Luk %A Kai-Pui Lam %B Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) %T Networks-On-Chip:\0The\0Quest\0for\0On-Chip\0Fault-Tolerant\0Communication %L Marculescu:2003:NOC %D 2003 %A Radu Marculescu %T Energy, Fault-Tolerance, and Scalability Issues in Designing Network-on-Chip %L Marculescu:2004:EFT %D 2004 %A Radu Marculescu %N 1 %J Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on %T Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives %L Marculescu:2009:ORP %D 2009 %K network synthesis, network-on-chipNoC design, circuit perspectives, communication infrastructure, communication paradigm, microarchitecture, network-on-chip architectures, on-chip components %V 28 %P 3-21 %A R. Marculescu %A U. Y. Ogras %A Li-Shiuan Peh %A N. E. Jerger %A Y. Hoskote %J Foundations and Trends in Electronic Design Automation %T The Chip Is the Network: Toward a Science of Network-on-Chip Design %L Marculescu:2009:TCI %D 2009", %P pp. 371-461 %A Radu Marculescu %A Paul Bogdan %B Field-Programmable Logic and Applications (FPL) %T Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs", %L Marescaux:2002:INE %D 2002 %C Montpellier %A T. Marescaux %A A. Bartic %A D. Verkest %A S. Vernalde %A R. Lauwereins %B Field-Programmable Logic and Applications %T Networks on Chip as Hardware Components of an OS for Reconfigurable Systems %L Marescaux:2003:NHC %D 2003 %S Lecture Notes in Computer Science %I Springer Berlin / Heidelberg %V 2778/2003 %P 595-605 %A T. Marescaux %A J-Y. Mignolet %A A. Bartic %A W. Moffat %A D. Verkest %A S. Vernalde %A R. Lauwereins %N 1 %J Integration, the VLSI journal %T Run-time support for heterogeneous multitasking on reconfigurable SoCs %L Marescaux:2004:RTS %D 2004 %I Elsevier Science Publishers B. V.", %V 38 %P 107-130 %A T. Marescaux %A V. Nollet %A J.-Y. Mignolet %A A. Bartic %A W. Moffat %A P. Avasare %A P. Coene %A D. Verkest %A S. Vernalde %A R. Lauwereins %B Parallel Computing Conference (ParCo %T Distributed congestion control for packet switched networks on chip %L Marescaux:2005:DCC %D 2005 %C Malaga, Spain %A Theodore Marescaux %A Anders Rangevall %A Vincent Nollet %A Andrei Bartic %A Henk Corporaal %B Proc. IEEE 3rd Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) %T Dynamic Time-Slot Allocation for QoS Enabled Networks on Chip %L Marescaux:2005:DTS %D 2005 %C New York, USA %I IEEE", %P 47-52 %A Theodore Marescaux %A Benjamin Bricke %A Peter Debacker %A Vincent Nollet Nollet %A Henk Corporaal %B nocs %T The impact of higher communication layers on NoC supported MP-SoC %L Marescaux:2007:IHC %D 2007", %A Theodore Marescaux %A Erik Brockmeyer %A Henk Corporaal %B nocs %T Mesh of Tree: Unifying mesh and MFPGA for better device performances %L Marrakchi:2007:MTU %D 2007", %A Zied Marrakchi %A Hayder Mrabet %A Christian Masson %A Habib Mehrez %B Proc. of the 39th Annual Intl. Symp. on Microarchitecture (MICRO) %T Coherence Ordering for Ring-based Chip Multiprocessors %L Marty:2006:COF %D 2006", %A Michael R. Marty %A Mark D. Hill %T Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platforms %L Mazhe:2007:SMR %D 2007", %I Springer %A Z. Ma %A P. Marchal %A D. P. Scarpazza %A P. Yang %A C. Wong %A J. I. Gomez %A S. Himpe %A C. Ykman-Couvreur %A F. Catthoor %B DATE '02: Proceedings of the conference on Design, automation and test in Europe %T Networks on Chip: A New Paradigm for Systems on Chip Design %L Micheli:2002:NOC %D 2002 %C Washington, DC, USA", %I IEEE Computer Society %P 418 %A G. de Micheli %A L. Benini %B nocs %T Approaching Ideal NoC Latency with Pre-Configured Routes %L Michelogiannakis:2007:AIN %D 2007", %A George Michelogiannakis %A Dionisios Pnevmatikatos %A Manolis Katevenis %N TRITA-IMIT-LECSR02:01 %T The Nostrum Protocol Stack and Suggested Services Provided by the Nostrum Backbone %L Millberg:2002:TNP %D 2002 %L Nostrum %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %C Stockholm, Sweden %O Draft v 0.1.48", %A Mikael Millberg %B Proceedings of the Design Automation and Test Europe Conference (DATE) %T Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip %L Millberg:2004:GBU %D 2004 %L Nostrum %A Mikael Millberg %A Erland Nilsson %A Rikard Thid %A Axel Jantsch %B Proceedings of the VLSI Design Conference %T The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip %L Millberg:2004:TNB %D 2004 %L Nostrum %C Mumbai, India %A Mikael Millberg %A Erland Nilsson %A Rikard Thid %A Shashi Kumar %A Axel Jantsch %B 2001 IEEE International Solid-State Circuits Conference, Digest of Technical Papers %T Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data %L Mizuno:2001:EIR %D 2001 %P 346-347, 464 %A M. Mizuno %A and W. J. Dally %A H. Onishi %B Proc.\0of\0the\0Intl.\0Symp.\0on\0System-on-Chip %T Comparative Analysis of Serial and Parallel Links in Networks-on-Chip %L Morgenshtein:2004:CAS %D 2004 %A A. Morgenshtein %A I. Cidon %A A. Kolodny %A R. Ginosar" %P 185-188 %B Proc.\0of\0the\011th\0IEEE\0Intl.\0Conf.\0on\0Electronics,\0Circuits\0and\0Systems\0(ICECS) %T Micro-modem\0-\0reliability\0solution\0for\0NoC\0communications %L Morgenshtein:2004:MRS %D 2004 %A A. Morgenshtein %A E. Bolotin %A I. Cidon %A R. Ginosar %A A. Kolodny" %P 483-486 %B Proceedings\0of\0the\0IEEE\0Intl.\0Symp.\0on\0Circuits\0and\0Systems\0(ISCAS) %T Low-Leakage Repeaters for NoC Interconnects %L Morgenshtein:2005:LLR %D 2005 %A A. Morgenshtein %A I. Cidon %A A. Kolodny %A R. Ginosar" %P 600-603 %N 1 %J IEEE Micro %T The Alpha 21364 network architecture %L Mukherjee:2002:TAT %D 2002 %V 22 %A S. S. Mukherjee %A P. Bannon %A S. Lang %A A. Spink %A D. Webb %B Proc. of the 31st Annual Intl. Symp. on Computer Architecture (ISCA) %T Low-Latency Virtual-Channel Routers for On-Chip Networks %L Mullins:2004:LLV %D 2004 %P 188-197 %A Robert D. Mullins %A Andrew F. West %A Simon W. Moore %T Asynchronous\0versus\0synchronous\0design\0techniques\0for\0NoCs %L Mullins:2005:AVS %D 2005 %A Robert D. Mullins %B Proc. of the 17th UK Async. Forum %T Selecting a Timing Regime for On-Chip Networks %L Mullins:2005:SAT %D 2005 %A Robert Mullins %A Jeong-Gun Lee %A Simon Moore %B Proceedings of the Intl. Symp. on System-on-Chip %T Minimising Dynamic Power Consumption in On-Chip Networks %L Mullins:2006:MDP %D 2006 %C Tampere, Finland", %A Robert Mullins %B Proceedings\0of\0the\011th\0Asia\0and\0South\0Pacific\0Design\0Automation\0Conference\0(ASP-DAC) %T The Design and Implementation of a Low-Latency On-Chip Network %L Mullins:2006:TDA %D 2006", %A Robert D. Mullins %A Andrew F. West %A Simon W. Moore %N 5 %T Analysis of Error Recovery Schemes for Networks on Chips %J Design \& Test of Computers %L Murali:2005:AOE %D 2005", %V 22 %P 434-442 %A S. Murali %A G. De Micheli %A L. Benini %A T. Theocharides %A N. Vijaykrishnan %A M. J. Irwin %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T A Methodology for Mapping Multiple Use-Cases on to Networks on Chip %L Murali:2006:AMF %D 2006 %A Srinivasan Murali %A Martijn Coenen %A Andrei R\uadulescu %A Kees Goossens %A Giovanni De Micheli %B Proc. Design Automation Conference. Asia and South Pacific (ASP-DAC) %T Mapping and Configuration Methods for Multi-Use-Case Networks on Chips %L Murali:2006:MAC %D 2006 %A Srinivasan Murali %A Martijn Coenen %A Andrei R\uadulescu %A Kees Goossens %A Giovanni De Micheli %B Proceedings of the 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers %T The\0Effect\0of\0Interconnect\0Design\0on\0the\0Performance\0of\0Large\0L2\0Caches %L Muralimanohar:2006:TEO %D 2006", %P %A N. Muralimanohar %A R. Balasubramonian %B Proceedings of the 34th International Symposium on Computer Architecture (ISCA-34) %T Interconnect\0Design\0Considerations\0for\0Large\0NUCA\0Caches %L Muralimanohar:2007:IDC %D 2007", %P %A N. Muralimanohar %A R. Balasubramonian %B Proc. of IEEE GLOBECOM %T Decomposed Crossbar Switches with Multiple Input and Output Buffers %L Nam:2001:DCS %D 2001", %A Seung Yeob Nam %A Dan Keun Sung %B Proceedings of the Second Intl. Conf. on Embedded Software and Systems (ICESS) %T Designing On-Chip Network Based on Optimal Latency Criteria %L Ngo:2005:DON %D 2005 %A Vu-Duc Ngo %A Huy Nam Nguyen %A Hae-Wook Choi %B Proc. of the 39th Annual Intl. Symp. on Microarchitecture (MICRO) %T ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers %L Nicopoulos:2006:VAD %D 2006", %A Chrysostomos A. Nicopoulos %A Dongkook Park %A Jongman Kim %A Narayanan Vijaykrishnan %A Mazin S. Yousif %A Chita R. Das %T Evaluation of Real-time Performance Models in Wormhole-routed On-chip Networks %L Nielsen:2005:EOR %L Nostrum %D 2005 %C Stockholm, Sweden %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %A Karl-Henrik Nielsen %N 3 %J Design Automation for Embedded Systems %T C-HEAP: A Heterogeneous Multi-processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems %L Nieuwland:2002:CHA %D 2002 %V 7 %P 233-270", %A Andre\*' Nieuwland %A Jeffrey Kang %A Om Prakash Gangwal %A Ramanathan Sethuraman %A Natalino Bus\'a %A Kees Goossens %A Rafael Peset Llopis %A Paul Lippens %T Design and Implementation of a Hot-potato Switch in a Network on Chip %L Nilsson:2002:DAI %D 2002 %L Nostrum %C Stockholm, Sweden %I Department of Microelectronics and Information Technology, Royal Institute of Technology, IMIT/LECS 2002-11 %A Erland Nilsson %B Proceedings of SSoCC %T Experiments of the Proximity Congestion Awareness with the Nostrum backbone %L Nilsson:2003:EOT %D 2003 %L Nostrum %C %A Erland Nilsson %B Proceedings of the Design Automation and Test Europe (DATE) %T Load distribution with the Proximity Congestion Awareness in a Network on Chip %L Nilsson:2003:LDW %D 2003 %L Nostrum %P 1126-1127 %A Erland Nilsson %A Mikael Millberg %A Johnny O\*:berg %A Axel Jantsch %B Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis %T Reducing Peak Power and Latency in 2-D Mesh NoCs using Globally Pseudochronous Locally Synchronous Clocking %L Nilsson:2004:RPP %D 2004 %L Nostrum %A Erland Nilsson %A Johnny O\*:berg %B Proceedings of the International Symposium on Signals, Circuits and Systems (ISSCS) %T Trading off power versus latency using GPLS clocking in 2D-mesh NoCs %L Nilsson:2005:TOP %D 2005 %L Nostrum %A Erland Nilsson %A Johnny O\*:berg %B Proceedings of the 41st annual conference on Design automation (DAC) %T Operating-System Controlled Network-on-Chip %L Nollet:2004:OSC %D 2004 %I ACM Press %P 256-259 %A Vincent Nollet %A The\*'odore Marescaux %A Diederik Verkest %A Jean-Yves Mignolet %A Serge Vernalde %B DATE '05: Proceedings of the conference on Design, Automation and Test in Europe %T Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles %L Nollet:2005:CRT %D 2005 %C Washington, DC, USA %I IEEE Computer Society %P 234-239 %A V. Nollet %A T. Marescaux %A P. Avasare %A J-Y. Mignolet %T Interconnect-Centric\0Design\0for\0Advanced\0SoC\0and\0NoC %L Nurmi:2004:ICD %D 2004 %I Kluwer Academic Publishers %E Jari Nurmi, Hannu Tenhunen and Axel Jantsch %B Networks on Chip %T Clocking Strategies for Networks on Chip %L Oberg:2003:CSF %D 2003 %L Nostrum %I Kluwer Academic Publishers %E Axel Jantsch and Hannu Tenhunen %P 153-172 %A Johnny O\*:berg %B Proc. IEEE/ACM Intl. Conf. on Computer Aided Design %T Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion %L Ogras:2005:ANA %D 2005 %C San Jose, CA %A Umit Y. Ogras %A Radu Marculescu %B Proc. Design, Automation and Test in Europe (DATE) Conf. %T Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach %L Ogras:2005:EPC %D 2005 %C Munich, Germany %A Umit Y. Ogras %A Radu Marculescu %B Proc. of the Intl. Conf. on Hardware/Software Codesign and System Synthesis %T Key Research Problems in NoC Design: A Holistic Perspective %L Ogras:2005:KRP %D 2005 %A Umit Y. Ogras %A Jingcao Hu %A Radu Marculescu %B Proc. Design, Automation and Test in Europe (DATE) Conf. %T Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip %L Ogras:2006:CAO %D 2006 %C Munich, Germany %A Umit Y. Ogras %A Radu Marculescu %A Hyung Gyu Lee %A Naehyuck Chang %N 7 %J IEEE Trans. on Very Large Scale Integration Systems, Special Section on Hardware/Software Codesign and System Synthesis %T "It's a small world after all": NoC Performance Optimization via Long Link Insertion %L Ogras:2006:ISW %D 2006 %V 14 %A Umit Y. Ogras %A Radu Marculescu %B Proc. ACM/IEEE Design Automation Conf. %T Prediction-based Flow Control for Network-on-Chip Traffic %L Ogras:2006:PFC %D 2006 %C San Francisco %A Umit Y. Ogras %A Radu Marculescu %B Proc. Design, Automation and Test in Europe (DATE) Conf. %T Analytical Router Modeling for Networks-on-Chip Performance Analysis %L Ogras:2007:ARM %D 2007 %C Nice, France %A Umit Y. Ogras %A Radu Marculescu %B Proc. IEEE/ACM Design Automation Conf. (DAC) %T Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip %L Ogras:2007:VFI %D 2007 %C San Diego %A Umit Y. Ogras %A Radu Marculescu %A Puru Choudhary %A Diana Marculescu %B Proc. Intl. Conf. on Hardware-Software Codesign and System Synthesis %T A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems %L Palesi:2006:AMF %D 2006", %C Seoul, Korea %A M. Palesi %A R. Holsmark %A S. Kumar %A V. Catania %B Proc. of the SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation %T A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures %L Palesi:2006:RTC %D 2006", %A M. Palesi %A S. Kumar %A R. Holsmark %B IFIP International Conference on Very Large Scale Integration (VLSI-SOC) %T Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures %L Pamunuwa:2003:LPA %D 2003 %L Nostrum %C Darmstadt, Germany %A D. Pamunuwa %A J. Öberg %A L. R. Zheng %A M. Millberg %A A. Jantsch %A H. Tenhunen %N 1 %J Integration - The VLSI Journal %T A Study on the Implementation of 2-D Mesh based Networks on Chip in the Nanoregime %L Pamunuwa:2004:ASO %D 2004", %L Nostrum %V 38 %P 3-17 %A Dinesh Pamunuwa %A Johnny O\*:berg %A Li-Rong Zheng %A Mikael Millberg %A Axel Jantsch %A Hannu Tenhunen %B nocs %T Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures %L Panades:2007:BFS %D 2007", %A Ivan Miro Panades %A Alain Greiner %N 5 %T Design, Synthesis, and Test of Network on Chips %J Design \& Test of Computers %L Pande:2005:DSA %D 2005", %V 22 %P 404-413 %A P. P. Pande %A G. De Micheli %A C. Grecu %A A. Ivanov %A R. Saleh %B Proc. of the 2006 Intl. Conf. on Dependable Systems and Networks %T Exploring Fault-Tolerant Network-on-Chip Architectures %L Park:2006:EFT %D 2006 %A Dongkook Park %A Chrysostomos Nicopoulos %A Jongman Kim %A N. Vijaykrishnan %A Chita R. Das %T Design and Implementation of a Fat Tree Network on Chip %L Pavia:2004:DAI %L Nostrum %D 2004 %C Stockholm, Sweden %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %A Juan Mata Pavia %I Eindhoven University of Technology", %T The\0`Asynchronous'\0Bibliography\0Homepage %L Peeters:2004:TAB %A Ad Peeters %B In Proc. of the 6th Int. Symp. on High-Performance Computer Architecture (HPCA) %T Flit-Reservation Flow Control %L Peh:2000:FRF %D 2000 %P 73-84", %A Li-Shiuan Peh %A William J. Dally %B Proc.\0International\0Symposium\0on\0High-Performance\0Computer\0Architecture\0(HPCA) %T A\0Delay\0Model\0and\0Speculative\0Architecture\0for\0Pipelined\0Routers %L Peh:2001:ADM %D 2001 %A Li-Shiuan Peh %A William J. Dally %P 255-266 %T Flow control and micro-architectural mechanisms for extending performance of interconnection networks %L Peh:2001:FCA %D 2001 %I Stanford University", %A Li-Shiuan Peh %T An Empirical Power Model of the Links and the Deflective Routing Switch in Nostrum %L Penolazzi:2005:AEP %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Sandro Penolazzi %B 21st International Conference on Computer Design %T Efficient Synthesis of Networks On Chip %L Pinto:2003:ESO %D 2003 %P 5 %A Alessandro Pinto %A Luca P. Carloni %A Alberto L. Sangiovanni-Vincentelli %B Proc. of ISVLSI Design %T Fault\0Tolerant\0Algorithms\0for\0Network-On-Chip\0Interconnect %L Pirretti:2004:FTA %D 2004 %P %A M. Pirretti %A G. M. Link %A R. R. Brooks %A N. Vijaykrishnan %A M. Kandemir %A M. J. Irwin %B nocs %T NoC Design and Implementation in 65nm Technology %L Pullini:2007:NSI %D 2007", %A Antonio Pullini %A Federico Angiolini %A Paolo Meloni %A David Atienza %A Srinivasan Murali %A Luigi Raffo %A Giovanni De Micheli %A Luca Benini %T Implementation of a JPEG Encoder on the Nostrum Network-on-Chip %L Qian:2005:IOA %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Xian Qian %B Proc. of the 23rd Intl. Conf. on Computer Design (ICCD) %T Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow %L Quinton:2005:AII %D 2005 %A Bradley R. Quinton %A Mark R. Greenstreet %A Steven J. E. Wilton %B Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation %T Communication Services for Networks on Chip %L Radulescu:2003:CSF %D 2004 %I Marcel Dekker %E Shuvra S. Bhattacharyya and Jr\*:gen Teich", %P 193-213 %A Andrei R\uadulescu %A Kees Goossens %N 1 %J IEEE Transactions on CAD of Integrated Circuits and Systems %T An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming %L Radulescu:2004:AEN %D 2005 %V 24 %P 4-17 %A Andrei R\uadulescu %A John Dielissen %A Santiago Gonza\*'lez Pestana %A Om Prakash Gangwal %A Edwin Rijpkema %A Paul Wielage %A Kees Goossens %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming %L Radulescu:2004:AEO %D 2004 %P 878-883 %A Andrei R\uadulescu %A John Dielissen %A Kees Goossens %A Edwin Rijpkema %B Proceedings of the 5th Workshop on Complexity-Effective Design, held in conjunction with ISCA-31 %T Microarchitectural\0Techniques\0to\0Reduce\0Interconnect\0Power\0in\0Clustered\0Processors %L Ramani:2004:MTT %D 2004", %P %A K. Ramani %A N. Muralimanohar %A R. Balasubramonian %N 3 %J Journal of Supercomputing %T Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture %L Rauwerda:2004:MWC %D 2004", %V 30 %P 263-282 %A G. K. Rauwerda %A P. M. Heysters %A G. J. M. Smit %B IEEE International Symposium on Circuits and Systems (ISCAS 2002) %T Parameter optimization tool for enhancing on-chip network performance %L Riihimaki:2002:POT %D 2002 %V 4 %P 61-64 %A J. Riihimaki %A E. Salminen %A K. Kuusilinna %A T. Hamalainen %B Proceedings of Progress 2001, 2nd Workshop on Embedded Systems %T A Router Architecture for Networks on Silicon %L Rijpkema:2001:ARA %D 2001", %C Veldhoven, the Netherlands %A Edwin Rijpkema %A Kees Goossens %A Paul Wielage %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip %L Rijpkema:2003:TOD %D 2003 %P 350-355 %A E. Rijpkema %A K. G. W. Goossens %A A. R\uadulescu %A J. Dielissen %A J. van Meerbergen %A P. Wielage %A E. Waterlander %N 5 %J IEE Proceedings: Computers and Digital Technique %T Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip %L Rijpkema:2003:TOI %D 2003 %V 150 %P 294-302 %A E. Rijpkema %A K. Goossens %A J. Dielissen A. R\uadulescu %A J. van Meerbergen %A P. Wielage %A E. Waterlander %B Proceedings\0of\0the\011th\0IEEE\0International\0Symposium\0on\0Asynchronous\0Circuits\0and\0Systems %T An\0Asynchronous\0Router\0for\0Multiple\0Service\0Levels\0Network\0on\0Chip %L Rostislav:2005:AAR %D 2005 %A Dobkin Rostislav %A Victoria Vishnyakov %A Eyal Friedman %A Ran Ginosar" %B Proc. European Conference on Circuit Theory and Design (ECCTD'01) %T Interconnect IP for Gigascale System-on-Chip %L Saastamoinen:2001:IIF %D 2001 %C Finland %P 281-284", %A Ilkka Saastamoinen %A Teemu Suutari %A Jouni Isoaho %A Jari Nurmi %B Proc. 1st International Workshop on Electronic Design, Test and Applications %T Interconnect IP Node for Future System-on-Chip Designs %L Saastamoinen:2002:IIN %D 2002 %P 116-120", %A Ilkka Saastamoinen %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Proc. IP Based SoC Design %T Proteo Interconnect IPs for Networks-on-Chip %L Saastamoinen:2002:PII %D 2002", %C Grenoble, France %A Ilkka Saastamoinen %A Mikko Alho %A Juha Pirttima\*:ki %A Jari Nurmi %B Networks on Chip %T An IP-Based On-Chip Packet-Switched Network %L Saastamoinen:2003:AIB %D 2003 %I Kluwer Academic Publishers %P 193-213", %E Axel Jantsch and Hannu Tenhunen %A Ilkka Saastamoinen %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Circuits and Systems, ISCAS '03. Proceedings of the 2003 International Symposium on %T Buffer\0Implementation\0for\0Proteo\0Networks-on-Chip %L Saastamoinen:2003:BIF %D 2003", %V 2 %P 113-116 %A I. Saastamoinen %A M. Alho %A J. Nunni %B Proc. of the Inter. Symp. on System-on-Chip %T Evaluating Application Mapping using Network Simulation %L Salminen:2003:EAM %D 2003", %C Tampere, Finland %A Tommi Salminen %A Juha-Pekka Soininen %B Proceedings of the 1st International Conference on Information \& Communication Technologies: from Theory to Applications (ICTTA'04) %T Formal Verification of On-Chip Networking %L Sammane:2004:FVO %D 2004", %A G. Al Sammane %A J. Schmaltz %A D. Borrione %B Proc. IEEE Int'l Symposium on Circuits and Systems (ISCAS) %T On the impact of traffic statistics on quality of service for networks on chip %L Santi:2005:OTI %D 2005", %A Stefano Santi %A Bill Lin %A Ljupco Kocarev %A Gian Mario Maggio %A Riccardo Rovatti %A Gianluca Setti %B Proc. of Formal Methods in Computer-Aided Design (FMCAD'04) %T A Functional Approach to the Formal Specification of Networks on Chip %L Schmaltz:2004:AFA %D 2004 %A J. Schmaltz %A D. Borrione %B Proceedings of the 5th International Workshop on the ACL2 Theorem Prover and its Applications (ACL2'04) %T A Functional Specification and Validation Model for Networks on Chip in the ACL2 Logic %L Schmaltz:2004:AFS %D 2004", %A J. Schmaltz %A D. Borrione %B Proc. of the 32nd Annual International Symposium on Computer Architecture (ISCA) %T Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks %L Seo:2005:NOW %D 2005 %P 432-443 %A Daeho Seo %A Akif Ali %A Won-Taek Lim %A Nauman Rafique %A Mithuna Thottethodi %B Proceedings of Design Automation Conference %T Addressing\0The\0System-on-a-Chip\0Interconnect\0Woes\0through\0Communication-based\0Design %L Sgroi:2001:ATS %D 2001", %P 667-672 %A M. Sgroi %A M. Sheets %A A. Mihal %A K. Keutzer %A S. Malik %A J. Rabaey %A A. Sangiovanni-Vincentelli. %B P %T Maximizing\0GFLOPS-per-Watt: High-Bandwidth, Low Power Photonic On-Chip Networks %L Shacham:2006:MGW %D 2006", %C IBM T. J. Watson Research Center, Yorktown Heights, New York %A Assaf Shacham %A Keren Bergman %A Luca P. Carloni %B nocs %T On the Design of a Photonic Network-on-Chip %L Shacham:2007:DPN %D 2007", %A Assaf Shacham %A Keren Bergman %A Luca P. Carloni %B Computer Architecture Letters %T Power-Efficient\0Interconnection\0Networks:\0Dynamic\0Voltage\0Scaling\0with\0Links %L Shang:2002:PEI %D 2002", %A Li Shang %A Li-Shiuan Peh %A Niraj K. Jha %B Proc. of the 37th MICRO %T Thermal\0Modeling,\0Characterization\0and\0Management\0of\0On-Chip\0Networks %L Shang:2004:TMC %D 2004", %A Li Shang %A Li-Shiuan Peh %A Amit Kumar %A Niraj K. Jha %B nocs %T A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network %L Shen:2007:NBM %D 2007", %A Wein-Tsung Shen %A Chih-Hao Chao %A Yu-Kuang Lien %A An-Yeu Wu %T Design and Implementation of the Resource-Network Interface for Networks-on-Chip %L Shipilov:2004:DAI %L Nostrum %D 2004 %C Stockholm, Sweden %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %A Dmitry Shipilov %B Proceedings of the International Conference on Dependable Systems and Networks %T Modeling\0the\0Effect\0of\0Technology\0Trends\0on\0the\0Soft\0Error\0Rate\0of\0Combinational\0Logic %L Shivakumar:2002:MTE %D 2002", %A P. Shivakumar %A M. Kistler %A S. Keckler %A D. Burger %A L. Alvisi %B Int. Conf. on Parallel Computing in Electrical Engineering (PARELEC) %T Communication Analysis for Network-on-Chip %L Siebenborn:2004:CAF %D 2004 %C Dresden, Germany %A A. Siebenborn %A O. Bringmann %A W. Rosenstiel %B Proceedings of Design, Automation and Test in Europe (DATE) Conference %T Managing\0Power\0Consumption\0in\0Networks\0on\0Chips %L Simunic:2002:MPC %D 2002", %A T. Simunic %A S. Boyd %B Proceedings of the CTIT workshop. Mobile Communications in perspective %T Towards A Model for Making A Trade-off Between QoS And Costs %L Smit:2001:TAM %D 2001 %A Lodewijk T. Smit %A Gerard J. M. Smit %A Paul J. M. Havinga %A Jos A. Huisken %A Kees G. W. Goossens %A John T. M. H. Dielissen %B Proc. of the Intl. Symp. on System-on-Chip (SoC 2005) %T Overview of the 4S project %L Smit:2005:OOT %D 2005 %C Tampere, Finland %P 70-73", %A Gerard Smit %A Eberhard Scu\*:ler %A Ju\*:rgen Becker %A Je\*'r0\*^me Que\*'vremont %A Werner Brugger %B Proc. of the 22nd Intl. Conf. on Computer Design (ICCD) %T Design-Space Exploration for Power-Aware On/Off Interconnection Networks %L Soteriou:2004:DSE %D 2004 %A Vassos Soteriou %A Li-Shiuan Peh %B International Conference on Measurement and Simulation of Computer and Telecommunication Systems (MASCOTS '06) %T A Statistical Traffic Model for On-Chip Interconnection Networks %L Soteriou:2006:AST %D 2006 %A Vassos Soteriou %A Hangsheng Wang %A Li-Shiuan Peh %B Design Automation Conference (DAC) %T Coding for system-on-chip networks: a unified framework %L Sridhara:2004:CFS %D 2004", %P 103-106 %A Srinivasa R. Sridhara %A Naresh R. Shanbhag %B In Proc. Design, Automation and Test in Europe (DATE) %T A low complexity heuristic for design of custom network-on-chip architectures %L Srinivasan:2006:ALC %D 2006", %A K Srinivasan %A K S Chatha %B IEEE International Conference on Computer-Aided Design (ICCAD) %T Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications %L Srivastava:2005:PAO %D 2005 %P 383-390 %A N. Srivastava %A K. Banerjee %B Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE) %T Networks on Chips for High-End Consumer-Electronics TV System Architectures %L Steenhof:2006:NOC %D 2006 %A Frits Steenhof %A Harry Duque %A Bjo\*:rn Nilsson %A Kees Goossens %A Rafael Peset Llopis %B Proceedings of Digital System Design, 8th Euromicro Conference (DSD'05) %T Predictable embedding of large data structures in multiprocessor networks-on-chip %L Stuijk:2005:PEO %D 2005", %P 388-395 %A S. Stuijk %A T. Basten %A B. Mesman %A M. C. W. Geilen %N ESR-2005-08 %T Time-Constrained Energy-Aware Routing and Scheduling of Network-on-Chip Communication %L Stuijk:2005:TCE %D 2005 %I Eindhoven University of Technology, Department of Electrical Engineering %A S. Stuijk %A A. H. Ghamarian %A T. Basten %A M. C. W. Geilen %A B. D. Theelen %T Simulation and Performance Evaluation for Networks on Chip %L Sun:2001:SAP %D 2001 %L Nostrum %C Stockholm, Sweden %I Department of Microelectronics and Information Technology, Royal Institute of Technology %O ELE/IMIT/2001-17 %A Yi-Ran Sun %B Proceedings of the IEEE NorChip Conference %T Simulation and Evaluation of a Network on Chip Architecture Using Ns-2 %L Sun:2002:SAE %D 2002 %L Nostrum %A Yi-Ran Sun %A Shashi Kumar %A Axel Jantsch .\" DATE 2006 %N 7 %J IEEE Journal of Solid-State Circuits %T Optimum\0Voltage\0Swing\0on\0On-Chip\0and\0Off-Chip\0Interconnect %L Svensson:2001:OVS %D 2001 %V 36 %P 1108-1112 %A C. Svensson %B IEEE Transactions on Computer %T Dynamically-Allocated\0Multi-Queue\0BUffers\0for\0VLSI\0Communication\0Switches %L Tamir:1996:DAM %D 1996", %V 6 %P 725-737 %A Y. Tamir %A G. L. Frasier %B The\031st\0Annual\0International\0Symposium\0on\0Computer\0Architecture\0(ISCA-31) %T Evaluation\0of\0the\0Raw\0Microprocessor:\0An\0Exposed-Wire-Delay\0Architecture\0for\0ILP\0and\0Streams", %L Taylor:2004:EOT %D 2004 %C Munich,\0Germany %A Michael Bedford Taylor %A others %N 3 %J IBM Journal of Research and Development %T The future of interconnection technology %L Theis:2000:TFO %D 2000", %V 44 %P 379-390 %A T. N. Theis %T A Network on Chip Simulator %L Thid:2002:ANO %D 2002 %L Nostrum, NNSE %I Department of Microelectronics and Information Technology, Royal Institute of Technology, IMIT/LECS 2002-17 %A Rikard Thid %B Proc. of Swedish System-on-Chip Conference, SSoCC'02 %T A simulator for On-Chip-Networks %L Thid:2002:ASF %L Nostrum, NNSE %D 2002 %C Falkenberg, Sweden %A R. Thid %A M. Millberg %B Proceedings of the IEEE NorChip Conference %T Evaluating NoC communication backbones with simulation %L Thid:2003:ENC %D 2003 %L Nostrum, NNSE %A Richard Thid %A Mikael Millberg %A Axel Jantsch %B Proc. of Swedish System-on-Chip Conference, SSoCC'03 %T Network on Chip Simulation using SystemC %L Thid:2003:NOC %L Nostrum, NNSE %D 2003 %C Eskilstuna, Sweden %A Rikard Thid %T Modeling of Dynamic Resource Allocation in a Network on Chip %L Thormann:2005:MOD %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Bjarke Thormann %B Proc. 7th Annual IEEE Intl. Workshop on High Level Design Validation and Test (HLDVT'02) %T VHDL-based\0Simulation\0Environment\0for\0Proteo\0NoC %L Tortosa:2002:VBS %D 2002 %P 1-6", %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Interconnect-Centric\0Design\0for\0Advanced\0SoC\0and\0NoC %T Arbitration and Routing Schemes for On-Chip Packet Networks %L Tortosa:2004:AAR %D 2004 %I Kluwer Academic Publishers %P 253-282", %E J. Nurmi, H. Tenhunen and A. Jantsch %A David Sigu\*:enza Tortosa %A Jari Nurmi %N 1 %J Integration, the VLSI Journal %T Issues\0in\0the\0development\0of\0a\0practical\0NoC:\0the\0Proteo\0concept %L Tortosa:2004:IIT %D 2004", %V 38 %P 95-105 %A David Sigu\*:enza-Tortosa %A Tapani Ahonen %A Jari Nurmi %B Proc. International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP) %T Packet Scheduling Configuration in Proteo Network-on-Chip %L Tortosa:2004:PSC %D 2004", %C Newcastle, UK %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Proc. International Conference on Parallel and Distributed Computing and Networks (PDCN'04) %T Packet Scheduling for Proteo Network-on-Chip %L Tortosa:2004:PSF %D 2004", %C Innsbruck, Austria %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Proc. International Symposium on System-on-Chip SoC2004 %T Topology Design for Global Link Optimization for Application Specific Network-on-Chip %L Tortosa:2004:TDF %D 2004 %C Tampere, Finland %P 135-138", %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Proc. Reconfigurable Communication-Centric SoCs (ReCoSoC 2005) %T System Monitoring and Reconfiguration in Proteo\0NoC %L Tortosa:2005:SMA %D 2005 %C Montpellier, France %P 99-104", %A David Sigu\*:enza Tortosa %A Jari Nurmi %B Proc. of the 11th IEEE European Test Symposium (ETS'06) %T A DFT Architecture for Asynchronous Networks-on-Chip %L Tran:2006:ADA %D 2006 %C Southampton, UK %P 219-224 %A Xuan-Tu Tran %A Jean Durupt %A ois Bertrand Franc\* %A Vincent Beroulle %A Chantal Robach %B The 12th IEEE European Test Symposium (ETS 2007) %T How to Implement an Asynchronous Test Wrapper for Network-on-Chip Nodes %L Tran:2007:HTI %D 2007 %C Freiburg, Germany %A Xuan-Tu Tran %A Jean Durupt %A ois Bertrand Franc\* %A Vincent Beroulle %A Chantal Robach %B Proc. of the Design, Automation and Test in Europe Conference (DATE) %T Leakage-Aware Interconnect for On-Chip Network %L Tsai:2005:LAI %D 2005", %A Yuh-Fang Tsai %A Vijaykrishnan Narayaynan %A Yuan Xie %A Mary Jane Irwin %B Proc. of the 39th Design Automation Conference %T Traffic\0Analysis\0for\0On-Chip\0Networks\0Design\0of\0Multimedia\0Applications %L Varatkar:2002:TAF %D 2002 %A Girish Varatkar %A Radu Marculescu %B Proceedings of the Great Lakes Symposium on VLSI %T Quality-of-Service\0and\0Error\0Control\0Techniques\0for\0Network-on-Chip\0Architectures %L Vellanki:2004:QOS %D 2004", %A P. Vellanki %A N. Banerjee %A K. Chatha %N 9 %J IEEE Communications Magazine %T Bringing Communication Networks On Chip: Test and Verification Implications %L Vermeulen:2003:BCN %D 2003 %O Guest editors: Dimitris Gizopoulos and Rob Aitken %V 41 %P 74-81 %A Bart Vermeulen %A John Dielissen %A Kees Goossens %A Calin Ciordas %B Proceedings of the IEEE NorChip Conference %T Low-Power and Error Coding for Network-on-Chip Traffic %L Vitkovski:2004:LPA %D 2004 %L Nostrum %A Arseni Vitkovski %A Raimo Haukilahti %A Axel Jantsch %A Erland Nilsson %T A Study on Power Consumption in the Nostrum Communication Network %L Vitkowski:2004:ASO %L Nostrum %D 2004 %C Stockholm, Sweden %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %A Arseni Vitkowski %B nocs %T Access Regulation to Hot-Modules in Wormhole NoCs %L Walter:2007:ARH %D 2007", %A Isaskhar Walter %A Israel Cidon %A Ran Ginosar %A Avinoam Kolodny %N 1 %J IEEE Computer Architecture Letters %T BENoC\0-\0A\0Bus-Enhanced\0Network\0on-Chip\0for\0a\0Power\0Efficient\0CMP %L Walter:2008:BEN %D 2008", %V 7 %A I. Walter %A I. Cidon %A A. Kolodny %B ACM/IEEE MICRO %T Orion:\0A\0Power-Performance\0Simulator\0for\0Interconnection\0Networks %L Wang:2002:OAP %D 2002", %A H. Wang %A X. Zhu %A L.-S. Peh %A S. Malik %B Proceedings of the 36th MICRO %T Power-Driven\0Design\0of\0Router\0Microarchitectures\0in\0On-Chip\0Networks %L Wang:2003:PDD %D 2003", %A Hang-Sheng Wang %A Li-Shiuan Peh %A Sharad Malik %B Proc. International Symposium on System-on-Chip SoC2004 %T A Synthesizable RTL Design of Asynchronous FIFO %L Wang:2004:ASR %D 2004 %C Tampere, Finland %P 123-128", %A Xin Wang %A Tapani Ahonen %A Jari Nurmi %B Proc. International Symposium on Signals Circuits and Systems (ISSCS) %T Asynchronous Network Node Design for Network-on-Chip %L Wang:2005:ANN %D 2005", %C Iasi, Romania %A Xin Wang %A David Sigu\*:enza Tortosa %A Tapani Ahonen %A Jari Nurmi %B Proc. of the Design, Automation and Test in Europe Conference (DATE) %T A Technology-aware and Energy-oriented Topology Exploration for On-Chip Networks %L Wang:2005:ATA %D 2005 %A Hangsheng Wang %A Li-Shiuan Peh %A Sharad Malik %B Euromicro Symposium On Digital System Design %T Networks on Silicon: Blessing or Nightmare? %L Wielage:2002:NOS %D 2002 %C Dortmund, Germany %O Keynote speech", %A Paul Wielage %A Kees Goossens %B Proceedings of Design Automation Conference (DAC) %T MicroNetwork-based integration for SOCs %L Wingard:2001:MBI %D 2001 %A D. Wingard %B Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - 12th Reconfigurable Architecture Workshop (RAW 2005), Denver, Colorado, USA %T An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip %L Wolkotte:2005:AEE %D 2005", %I IEEE Computer Society %P 155 %A P. T. Wolkotte %A G. J. M. Smit %A G. K. Rauwerda %A L. T. Smit %B Proceedings of the 15th International Conference on Field Programmable Logic and Applications 2005 (FPL 2005), Tampere, Finland %T Energy-Efficient NoC for Best-Effort Communication %L Wolkotte:2005:EEN %D 2005", %I IEEE Circuits and Systems Society %P 197-202 %E T. Rissa and P. Leong %A P. T. Wolkotte %A G. J. M. Smit %A J. E. Becker %B Proc. of the Intl. Symp. on System-on-Chip (SoC 2005) %T Energy Model of Networks-on-Chip and a Bus %L Wolkotte:2005:EMO %D 2005 %I IEEE %P 82-85 %E J. Nurmi and T. D. Hamalainen %A P. T. Wolkotte %A G. J. M. Smit %A N. K. Kavaldjiev %A J. E. Becker %A J. Becker %B nocs %T Fast, Accurate and Detailed NoC Simulations %L Wolkotte:2007:FAD %D 2007", %A Pascal T. Wolkotte %A Philip K. F. Holzenspies %A Gerard J. M. Smit %B Proceedings of The 15th International Symposium on System Synthesis %T An\0Adaptive\0Low-Power\0Transmission\0Scheme\0for\0On-Chip\0Networks %L Worm:2002:AAL %D 2002", %P 92-100 %A Frederic Worm %A Paolo Ienne %A Patrick Thiran %A Giovanni De\0Micheli %N 1 %T A Robust Self-calibrating Transmission Scheme for On-Chip Networks %J IEEE Transactions on VLSI %L Worm:2005:ARS %D 2005", %V 13 %P 126-139 %A F. Worm %A P. Ienne %A P. Thiran %A G. De Micheli %B nocs %T Implementing DSP Algorithms with On-Chip Networks %L Wu:2007:IDA %D 2007", %A Xiang Wu %A Tamer Ragheb %A Yehia Massoud %A Adnan Aziz %B Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES) %T Wave pipelining for application-specific networks-on-chips. %L Xu:2002:WPF %D 2002 %P 198-201 %A Jiang Xu %A Wayne Wolf %B The 11th Symposium On High Performance Interconnects %T A\0Wave-Pipelined\0On-chip\0Interconnect\0Structure\0for\0Networks-on-Chips %L Xu:2003:AWP %D 2003", %P 10 %A Jiang Xu %A Wayne Wolf. .\" http://lsi.epfl.ch/page13139.html %B Design, Automation and Test in Europe Conference and Exposition (DATE 2004) %T A Case Study in Networks-on-Chip Design for Embedded Video %L Xu:2004:ACS %D 2004 %P 770-777 %A Jiang Xu %A Wayne Wolf %A Jo\*:rg Henkel %A Srimat T. Chakradhar %A Tiehan Lv %B Proc. of 2nd Working Conference on Asynchronous Design Methodologies %T Designing an asynchronous pipeline token ring interface %L Yakovlev:1995:DAP %D 1995 %C London %I IEEE Comp. Society Press %P 32-41 %A A. Yakovlev %A V. Varshavsky %A V. Marakhovsky %A A. Semenov %N 1 %J IEEE Design and Test of Computers %T High level modelling and design of asynchronous interface logic %L Yakovlev:1995:HLM %D 1995 %V 12 %A A. Yakovlev %A A. Koelmans %A L. Lavagno %B Proc. of the 8th Intl. Symp. on Parallel Architectures, Algorithms and Networks (ISPAN) %T Fault-tolerant\0routing\0schemes\0in\0RDT(2,2,1)/alpha-based\0interconnection\0network\0for\0networks-on-chip\0design %L Yang:2005:FTR %D 2005", %A Mei Yang %A Tao Li %A Yinglao Jiang %A Yulu Yang %B Proceedings. 39th Design Automation Conference %T Analysis of power consumption on switch fabrics in network routers %L Ye:2002:AOP %D 2002 %P 524-529 %A T. T. Ye %A L. Benini %A G. De Micheli %B Proc. Design Automation and Test in Europe %T Packetized\0On-Chip\0Interconnect\0Communication\0Analysis\0for\0MPSoC %L Ye:2003:POC %D 2003", %P 344-349 %A Terry Tao Ye %A Luca Benini %A Giovanni De Micheli %T Design and Implementation of a Wormhole Router Supporting Multicast for Networks on Chips %L Yin:2005:DAI %L Nostrum %D 2005 %I Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH) %A Bei Yin %B Proceedings of the International Symposium on System-on-Chip %T Design-Time Application Exploration for MP-SoC Customized Run-Time Management %L Ykman:2005:DTA %D 2005 %C Tampere, Finland %P 66-73 %A Ch. Ykman-Couvreur %A E. Brockmeyer %A V. Nollet %A Th. Marescaux %A Fr. Catthoor %A H. Corporaal %B soc %T Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management %L Ykman:2006:FMD %D 2006 %C Tampere, Finland %P 195-198 %A Ch. Ykman-Couvreur %A V. Nollet %A Fr. Catthoor %A H. Corporaal %B Proceedings of the International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS) %T Pareto-based application specification for MP-SoC Customized Run-Time Management %L Ykman:2006:PBA %D 2006 %C Samos, Greece %P 78-84 %A Ch. Ykman-Couvreur %A V. Nollet %A Th. Marescaux %A E. Brockmeyer %A Fr. Catthoor %A H. Corporaal %B Electronic Notes in Theoretical Computer Science, 200(1) %T Performance Evaluation of Elastic GALS Interfaces and Network Fabric %L You:2008:PEE %D 2008 %I Elsevier", %P 17-32 %A Junbok You %A Yang Xu %A Hosuk Han %A Kenneth S. Stevens %B IEEE International Solid-State Circuits Conference, (ISSCC '06) %T An Asynchronous Array of Simple Processors for DSP Applications %L Yu:2006:AAA %D 2006", %A Zhiyi Yu %A Michael Meeuwsen %A Ryan Apperson %A Omar Sattari %A Michael Lai %A Jeremy Webb %A Eric Work %A Tinoosh Mohsenin %A Mandeep Singh %A Bevan M. Baas %B Proceedings of the WVLSI %T Interconnect\0Architecture\0Exploration\0for\0Low-Energy\0Reconfigurable\0Single-Chip\0DSPs %L Zhang:1999:IAE %D 1999", %A H. Zhang %A M. Wan %A V. George %A J. Rabaey %B Proc. of IEEE Intl. Parallel and Distributed Processing Symposium %T A study of the On-Chip Interconnection Network for the IBM\0Cyclops64 Multi-Core Architecture %L Zhang:2006:ASO %D 2006", %C Rhodes Island, Greece %A Yingping Zhang %A Taikyeong Jeong %A Fei Chen %A Ronny Nitzsche %A Guang R. Gao %T Evaluation of Deflection-routed On-Chip Networks %L Zhong:2005:EOD %L Nostrum %D 2005 %C Stockholm, Sweden %I School for Information and Communication Technology, Royal Institute of Technology %A Mingchen Zhong %T Fault Modelling and Error-Control Coding in a Network-on-Chip %L Zimmer:2002:FMA %D 2002 %L Nostrum %C Stockholm %I Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH), IMIT/LECS 2002-26 %A Heiko Zimmer %B Proceedings of the CODES-ISSS Conference %T A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip %L Zimmer:2003:AFM %D 2003 %L Nostrum %A Heiko Zimmer %A Axel Jantsch %B Interconnect-Centric Design for Advanced SoCs and NoCs %T Error-tolerant Interconnect Schemes %L Zimmer:2004:ETI %D 2004 %L Nostrum %I Kluwer Academic Publisher %E Jari Nurmi, Hannu Tenhunen and Axel Jantsch %A Heiko Zimmer %A Axel Jantsch