On-Chip Network Research Resources Page

Welcome

Welcome to the on-chip network research resources page. Our aim is to provide a useful resource for the on-chip network research community.

Why On-Chip Networks?

The construction of efficient chip-wide communication infrastructures is becoming increasingly important for many reasons, here are some:

  • The negative effect of technology scaling on global interconnects
  • Growing system complexity
  • The need to manage power and thermal limits (task migration, dynamic mapping, throttling...)
  • The need to construct flexible multi-use designs and platforms
  • Growing interconnect verification challenges as fabrication technology scales
  • Increased dependence on fault-tolerant mechanisms as feature sizes reduce
  • Increasing use of parallel architectures (e.g. chip multiprocessors, tiled processors and beyond)

For introductory material look at the introduction section of the bibliography browser.

News

Aug'09 sub. deadline NoCArc 2009 at MICRO-42
Nov 2008 First International Workshop on Network on Chip Architectures (with MICRO-41)
June 2008 DAC Workshop: Diagnostic Services in Network-on-Chips (DSNOC)
April 2008 ASYNC 2008 and NOCS 2008. To be collocated in Newcastle (UK) with jointly coordinated keynote lectures, tutorials, exhibitions and social events.
New Book "Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms", Ma, Z., Marchal, P., Scarpazza, D.P., Yang, P., Wong, C., Gomez, J.I., Himpe, S., Ykman-Couvreur, C., Catthoor, F.
CFP HiPEAC Interconnection Network Architectures Workshop
July 2007 Netmaker interconnection network library
May 2007 IBM self-assembles airgaps around on-chip interconnect
March 2007 Prof. Agarwal (MIT/Tilera) at the Multicore Expo.
February 2007 Nextgen Multicore NoCs, Article at embedded.com by Luca Benini and Giovanni De Micheli
January 2007 HP's Nanoscale Crossbar
Paper: Nano/CMOS architectures using field-programmable nanowire interconnect
(HP Link)
Sept. 2006 Intel's 80 core research processor (on-chip network, stacked dies)
(Intel Link)
Journal CFP Transactions on HiPEAC (March 1st 2007)

Some Recent Additions to our Network-on-Chip Bibliography...

Jongman Kim, C. Nicopoulos and Dongkook Park, A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Tobias Bjerregaard and Shankar Mahadevan, A Survey of Research and Practices of Network-on-Chip
F. Li, M. Kandemir and I. Kolcu, "Exploiting Software Pipelining for Network-on-Chip Architectures"