Run W+RWC+lwsync+addr+po in model, using ppcmem
PPC W+RWC+lwsync+addr+po "LwSyncdWW Rfe DpAddrdR Fre PodWR Fre" Cycle=Rfe DpAddrdR Fre PodWR Fre LwSyncdWW { 0:r2=x; 0:r4=y; 1:r2=y; 1:r5=z; 2:r2=z; 2:r4=x; } P0 | P1 | P2 ; li r1,1 | lwz r1,0(r2) | li r1,1 ; stw r1,0(r2) | xor r3,r1,r1 | stw r1,0(r2) ; lwsync | lwzx r4,r3,r5 | lwz r3,0(r4) ; li r3,1 | | ; stw r3,0(r4) | | ; exists (1:r1=1 /\ 1:r4=0 /\ 2:r3=0)