Test WRC+addr+sync

Run WRC+addr+sync in model, using ppcmem

PPC WRC+addr+sync
"Rfe DpAddrdW Rfe SyncdRR Fre"
Cycle=Rfe SyncdRR Fre Rfe DpAddrdW
{
0:r2=x;
1:r2=x; 1:r5=y;
2:r2=y; 2:r4=x;
}
 P0           | P1            | P2           ;
 li r1,1      | lwz r1,0(r2)  | lwz r1,0(r2) ;
 stw r1,0(r2) | xor r3,r1,r1  | sync         ;
              | li r4,1       | lwz r3,0(r4) ;
              | stwx r4,r3,r5 |              ;
exists
(1:r1=1 /\ 2:r1=1 /\ 2:r3=0)