Test LB+isync+addr

Run LB+isync+addr in model, using ppcmem

PPC LB+isync+addr
"ISyncdRW Rfe DpAddrdW Rfe"
Cycle=Rfe ISyncdRW Rfe DpAddrdW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=x;
}
 P0           | P1            ;
 lwz r1,0(r2) | lwz r1,0(r2)  ;
 isync        | xor r3,r1,r1  ;
 li r3,1      | li r4,1       ;
 stw r3,0(r4) | stwx r4,r3,r5 ;
exists
(0:r1=1 /\ 1:r1=1)