Test LB+ctrlisync+po

Run LB+ctrlisync+po in model, using ppcmem

PPC LB+ctrlisync+po
"DpCtrlIsyncdW Rfe PodRW Rfe"
Cycle=Rfe PodRW Rfe DpCtrlIsyncdW
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=x;
}
 P0           | P1           ;
 lwz r1,0(r2) | lwz r1,0(r2) ;
 cmpw r1,r1   | li r3,1      ;
 beq  LC00    | stw r3,0(r4) ;
 LC00:        |              ;
 isync        |              ;
 li r3,1      |              ;
 stw r3,0(r4) |              ;
exists
(0:r1=1 /\ 1:r1=1)