I am currently working as a Research Assistant in the DOME (Delaying and Overcoming Microprocessor Errors) project. I am looking at Processor Ageing, caused by hard faults, and to find ways on how we can delay the occurrence of errors. There is little knowledge of how the applications that we run on our computing systems will affect transistor wearout. I am addressing this by constructing models for ageing of internal processor structures, and also software solutions to reduce the wearout that an application causes as it runs.
Comparative Architecture, part II, Lent term 2014, Computer Laboratory.
- Sep 2009-Feb 2012 - MSc. in Computer Engineering-Architecture, Shahid Beheshti University (Previously, National University of Iran),Tehran,Iran
- Sep 2004-Sep 2008 - BSc. in Computer Engineering-Hardware, Tarbiat Dabir Shahid Rajaee University,Tehran,Iran
My MSc thesis title was "Parallelizing Multi-level placement algorithms on Multi-core systems", supervised by Dr Ali Jahanian. For my Masters thesis, I worked on parallelising the Capo Placer and Dragon Placer Placement Algorithms. I also worked on parallelisation of Multiple Markov Chains Algorithm for EduCAD VLSI CAD training tool Placement, and we developed our own parallelised PARSA placement VLSI CAD algorithm.
For my Bachelors, I worked with the researchers at Control and Intelligent Processing Center of Excellence- University of Tehran. My work was to implement on-chip information fusion operators, a model driven approach, which was a fully automated toolbox in MATLAB/Simulink environment and on an Altera Cyclone-II FPGA.
- Computer Architecture
- Fault Tolerance
- VLSI Physical Design Algorithms
- Synthesis and Optimisation of Digital Circuits
In addition to my research, I am also a committee member of Women@CL to promote women leadership and engagement in computer science.
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Information provided by Negar Miralaei