Papers and Publications

Here is a list of documents I've produced while in academia.

PhD Related

• Managing a Reconfigureable Processor in a General Purpose Workstation Environment
  Accepted to DATE'03. Published by IEEE Computer Society.
  Abstract: Reconfigurable processor hybrids are becoming an accepted solution in the embedded systems domain, but have yet to gain acceptance in the general purpose workstation domain. One problem with current solutions is their lack of support for the dynamic workloads and resource demands of a general purpose workstation. In this paper we describe and demonstrate a reconfigurable processor architecture that lets the operating system dynamically share the FPL resource between a set of applications without the management overheads negating the benefit of having the extra resource.
  Paper: The PDF of the paper (Copyright 2003 IEEE) can be downloaded here.
  
  
• Initial Analysis of the Proteus Architecture
  Accepted to FPL'01.Published by Springer-Verlag.
  Abstract: The Proteus Architecture proposed a general purpose microprocessor with reconfigurable function units. The ProteanARM represents an ARM-based realisation of this concept. This paper describes the initial details of the ProteanARM architecture and demonstrates some performance benefits gained through the use of custom function units. Our examples show a promising performance increase compared to a standard ARM processor, with reconfiguration costs being quickly amortised.
  Paper: The PDF of the paper (Copyright 2001 Springer-Verlag) can be downloaded here.
  Poster:The PDF for an A0 version of my poster can be downloaded here.
  
  
• Reconfigurable Functionality - The OS Perspective
  Talk given at Dynamically Reconfigurable Architectures held at Schloss Dagstuhl.
  Abstract:In an attempt to bring FPL to the masses, there have been several attempts to introduce FPL into a desktop machine, ranging from simply an FPGA on a PCI card, to placing FPL inside the heart of a microprocessor. However, most of this work concentrates on the issues at the bit level, spending little effort considering how this new resource will be manage by the software which runs upon it.

  An Operating System (OS) provides an application with an abstraction of the hardware environment, but the hardware in turn needs to support this abstraction (e.g hardware support for virtual memory). In this talk I present some of the issues I see as an operating systems person with the current attempts to integrate FPL into the desktop machine. This will include an outline of the OSs duties in managing a resource, then outlining some of the problems that will need low-level aid, thus requiring support from the integrated hardware. It is likely that designers of integrated systems will need to provide this support if desktop FPL implementations are to become prevalent.
  Presentation: The PDF version of the presentation slides can be downloaded here.

• The Proteus Processor - A Conventional CPU with Reconfigurable Functionality
  Accepted to FPL'99. Published by Springer-Verlag.
  Abstract: This paper describes the starting position for research beginning at the Department of Computing Science, University of Glasgow. The research will investigate a novel microprocessor design incorporating reconfigurable logic in its ALU, allowing the processor's function units to be customised to suit the currently running application. We argue that this architecture will provide a performance gain for a wide range of applications without additional programmer effort. The paper gives some background information into similar research, argues the benefits of this idea compared to current research, and lists some of the questions that need to be answered to make this idea a reality. We end by specifying the initial work plan for the project.
  Paper: The PDF of the paper (Copyright 1999 Springer-Verlag) can be downloaded here.
  Poster: The PDF for an A4 version of my poster can be downloaded here.
  
  

Pegasus II Related

• ESPRIT LTR 21917 (Pegasus II) Deliverable 4.5.2: Unix functionality
  Milestone deliverable report for the Pegasus II project. Co-authored with Rolf Neugebauer. PDF version.
  Abstract: Traditional operating systems present fixed, high-level abstractions to application developers and users. These are part of standard APIs, such as POSIX or X/OPEN, which are typically implemented as a thin library layer on top of monolithic kernels. Recent efforts in operating system research, however, have focussed on providing more flexibility and new functionality to applications by lowering the abstraction level to a minimal kernel interface. Higher-level abstractions are provided through user-level servers or, more recently, through shared libraries. These library based operating systems allow the design and implementation of arbitrary high-level abstractions as user-level shared libraries on top of a minimal kernel interface.

  Nemesis is a library based operating system which offers genuine support for multi-media data stream types by providing Quality of Service guarantees for all shared resources in the system. In Nemesis, the libraries implementing the high level abstractions are carefully designed to avoid interactions between different processes for shared state. Abstractions which rely on traditional stateful APIs are handled using library componets called personalities, described in deliverable 4.5.1.

  This deliverable report describes the design and implementation of a personality offering Unix-like functionality for the Nemesis operating system. This effort was motivated on two grounds: first, to research the techniques and feasibility of providing such functionality in a single address space system such as Nemesis, and second, by the desire to take advantage of the vast amount of existing application code available for Unix systems.
  Presentation: A presentation of this work was given at Multi-Service Networks '99. The PDF version of the slides can be reached here.

Others

• Postscript Rendering with Virtual Hardware
  By Satnam Singh, John Patterson, Jim Burns, and Michael Dales.
  Accepted to FPL'97. Published by Springer-Verlag.
  Abstract: This paper presents the techniques being developed to design a high speed PostScript rendering engine using virtual hardware. The problem of rendering PostScript for high quality colour correct printed output is decomposed into a series of tasks which can be performed in sequence on one FPGA, making this application very suitable for implementation with virtual hardware. The virtual hardware solution promises superior performance and much lower cost than existing PostScript rendering systems.
  Paper: The PDF of the paper (Copyright 1997 Springer-Verlag) can be downloaded here.