Last modified on Mon Feb 2 14:50:33 GMT 2004
From 1999 to 2003 I worked on my PhD investigating operating system support for reconfigurable processors in a workstation environment. Although reconfigurable processors are not new, so far they have only been applied to the embedded systems domain. In this work I looked at the constraints placed upon such a device by the dynamic and unpredictable workload common to workstation systems, where multiple processes are being run concurrently for multiple users. The research was supported by EPSRC and Xilinx Edinburgh.
The first stage of this work was to produce a reconfigurable processor architecture that was suited to being managed by an operating system. Existing architectures, though well suited to embedded systems, lack an easy path with low run-time cost to easily sharing the reconfigurable logic resource securely between multiple processes. In a workstation environment applications are typically decoupled from their resources through virtualisation, and to achieve this without a performance hit requires hardware support.
To this end we created the Proteus Architecture (see papers FPL'99 and FPL'01) which provides a reconfigurable function unit on the processor, similar to existing integer and floating point units, which contains a register file and a set of reconfigurable logic blocks called Programmable Function Units (PFUs) into which new instructions can be loaded at run time. In addition to the PFUs, the new unit includes hardware support for virtualisation, dynamically dispatching to a software alternative implementation when no PFUs are free, and usage statistics to allow the OS to better managed the PFUs.
An ARM based example of the Proteus Architecture, referred to as the ProteanARM, has been simulated using an extention of the C++ ARM model SWARM. This has been used to demonstrate that the architecture is suitable for accelerating individual applications through the use of custom instructions (see paper DATE'03).
Following on from the architecture support, we looked at how an operating system could manage the set of PFUs on the processor. We created an operating system, called POrSCHE (Proteus Operating System and Configurable Hardware Environment), which provides a basic pre-emptive multitasking kernel (as would be found in a workstation class operating system) along with a Custom Instruction Scheduler (CIS). The CIS is used by applications to register custom instructions, and it is the job of the CIS to ensure that custom instructions are available when required by an application. The CIS is responsible for scheduling the custom instructions into PFUs on a dynamic, demand driven basis. Thanks to the virtualisation support in the hardware, applications need not be aware of which PFU their instructions are loaded into.
The problem in such a system is that when the number of PFUs required by running applications exceeds demand, the operating system will need to either swap circuits on and off as application context switches occur, or cause some applications to run in software rather than hardware. Both of these options will result in a performance loss for the system. We have demonstrated, using this operating system running on top of the SWARM based simulator, that it is possible to multiplex multiple applications' PFU requirements, even at times of high PFU contention, without negating the benefit of the reconfigurable logic resource. That is, the overheads of either swapping circuits or moving some applications to software do not exceed the performance gained from custom hardware.
The final level of problem is ensuring that applications can make use of the new resource easily, lest programmers find it too difficult to work with. The idea is that the traditional compile and link flow, along with concepts such as static and shared libraries, should be applicable usable with the new resource. We have proposed a suitable solution to this problem by looking at how existing compilers work, allow application programmers to specify a new instruction and then just invoke it, leaving the lower levels to sort out how the instruction is registered with the OS and then invoked.
I was awarded my PhD in August 2003. Currently there have been three papers published based on this work: two poster papers at FPL'99 and FPL'01, and a conference paper at DATE'03.
If you have any queries about this work, then please feel free to get in touch with me, either by the email address at the bottom of the page, or by the other addresses listed on my home page.
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This site is Copyright 2003, 2004 Michael Dales Last modified on Mon Feb 2 14:50:33 GMT 2004 |