The Semantic Challenge of Verilog HDL (talk)

Overhead projector transparencies for a talk based on the paper The Semantic Challenge of Verilog HDL are available as a single postscript file or as separate files for each transparency:
  1. The Semantic Challenge of Verilog HDL
  2. Modern HDLs
  3. Uses of HDLs
  4. Verilog HDL
  5. Overview of Verilog (1)
  6. Overview of Verilog (2)
  7. Events and Scheduling
  8. Zero-delay Assignments
  9. Example Assignments
  10. Timing Control
  11. Timing Controlled Assignments: Continuous Assignments
  12. Timing Controlled Assignments: Procedural Assignments
  13. Inertial versus Transport Delay
  14. Inertial Assignment (in VHDL but not Verilog)
  15. More on Event Control
  16. Semantics of Continuous Assignment
  17. Verilog's Data Types
  18. Complete Example: a Multiplier
  19. The Multiplier in Verilog
  20. A Complete Module
  21. Test Data
  22. Test Harness
  23. Output from Simulator
  24. Semantic Challenges
  25. Formal Semantics of Verilog
  26. Simplified Semantics
  27. A Minimal Simulation Calculus
  28. Equivalence Between Modules
  29. Correctness of Synthesisers
  30. Example Synthesisable Module
  31. Example of Design Synthesis
  32. Conclusions