Khilan Gudka

Office 558C, Huxley Building,
Department of Computing,
Imperial College London,
180 Queen's Gate,
London SW7 2AZ, UK

Email: firstname@doc.ic.ac.uk

*** I am now a Research Associate at the University of Cambridge Computer Laboratory. You can find my new homepage here. ***

*** I have recently completed my PhD, entitled "Lock Inference for Java." You can find my thesis here. ***

Biography

I am a final year PhD student supervised by Professor Susan Eisenbach and Professor Sophia Drossopoulou of the SLURP group at the Department of Computing, Imperial College London.

My research is generously funded by Microsoft Research Cambridge as part of their PhD Scholarship programme. My sponsor at Microsoft is Tim Harris.

Prior to this, I completed a four-year undergraduate MEng Computing degree also at the department. During my final year, I had the fortune of working with David Cunningham on atomicity for concurrent programs.

Research

Atomicity provides strong guarantees against errors caused by unanticipated thread interactions, but is difficult for programmers to implement directly with low-level concurrency primitives. This has led to research on automated techniques for providing atomicity, such as using transactional memory (TM). However, this approach has the limitation of not being able to support system calls (without serialising all atomic sections).

Lock inference is another technique, which statically infers locks sufficient to ensure atomicity without causing deadlock. One possibility is to acquire a global lock before executing each atomic section, ensuring they execute in mutual exclusion. However, this cripples concurrency as non-interfering atomic sections cannot execute in parallel.

My research looks at inferring fine-grained locks to allow as much concurrency as possible, while balancing the overheads of lock acquisition and deadlock prevention. I am also interested in a hybrid implementation of transactional memory with lock inference.

Relevant areas:

  • Lock inference
  • Transactional memory
  • Program analysis
  • Parallel programming models
  • Parallel architectures

Publications

Posters

Reports