⇡ lowRISC tagged memory tutorial
Simulating the Verilog (FPGA target) generated by Chisel
Chisel can generate Verilog for an FPGA target. This Verilog RTL can also be simulated with the Synopsys VCS tool (other Verilog simulators are not supported at present).
To generate the VCS simulator binary:
# requirements: riscv-gnu-toolchain, riscv-fesvr
# set up the RISCV environment variables
# set up the VCS environment variables
cd $TOP/fsim
make
This will generate a simulator called simv-DefaultFPGAConfig
assuming the Default configuration is used. As was the case for the
Chisel emulator, for simulating a different lowRISC configuration,
TAGW32S2T4FPGA for example, you can either change the CONFIG variable
in the Makefile or temporarily run make as:
CONFIG=TAGW32S2T4FPGA make
However, if you decide to the temporary CONFIG target, you need to add the temporary target before all make commands, such as make run.
Note: Only configurations labelled with FPGA can be used when
simulating RTL generated for an FPGA. For a certain Chisel/VLSI
target TARGET
, the corresponding FPGA target will be labelled as
TARGETFPGA
. See lowrisc-chip/src/main/scala/PublicConfigs.scala
for more details.
If the VCD (or VPD) waveform is needed, run the following instead.
# set up the RISCV environment variables
# set up the VCS environment variables
cd $TOP/fsim
make debug
There are multiple pre-build test cases to test the Rocket Core. To run the pre-built tests:
# set up the RISCV environment variables
# set up the VCS environment variables
# build and run the basic ISA test cases
make run-asm-tests
# build and run the bench-mark tests
make run-bmarks-test
# build and run the tag cache tests
make run-tag-tests
# build and run all the above tests in a single run
make run
# when VCD is required
make run-asm-tests-vcd
make run-bmarks-test-vcd
make run-tag-tests-vcd
# all tests in a single run
make run-vcd
# when VPD is required
make run-asm-tests-vpd
make run-bmarks-test-vpd
make run-tag-tests-vpd
# all tests in a single run
make run-vpd
To simulate the hello program in the three different modes (assuming the correct type of binary has been produced, i.e. .bare, .pk and .linux):
Bare metal mode
Requirements: riscv-isa-sim
, riscv-fesvr
, riscv-gnu-toolchain
# set up the RISCV environment variables
# set up the VCS environment variables
# No VCD/VPD file
./simv-DefaultFPGAConfig -q +ntb_random_seed_automatic +dramsim \
+verbose +max-cycles=100000000 $TOP/riscv-tools/hello/hello.bare \
3>&1 1>&2 2>&3 | spike-dasm > hello.out && [ $PIPESTATUS -eq 0 ]
# VCD file
./simv-DefaultFPGAConfig-debug -q +ntb_random_seed_automatic \
+dramsim +verbose +vcdfile=hello.vcd +max-cycles=100000000 \
$TOP/riscv-tools/hello/hello.bare 3>&1 1>&2 2>&3 | \
spike-dasm > hello.out && [ $PIPESTATUS -eq 0 ]
# VPD file
./simv-DefaultFPGAConfig-debug -q +ntb_random_seed_automatic \
+dramsim +verbose +vcdplusfile=hello.vpd +max-cycles=100000000 \
$TOP/riscv-tools/hello/hello.bare 3>&1 1>&2 2>&3 | \
spike-dasm > hello.out && [ $PIPESTATUS -eq 0 ]
With proxy kernel and newlib
Requirements: riscv-isa-sim
, riscv-fesvr
, riscv-pk
, riscv-gnu-toolchain
# set up the RISCV environment variables
# set up the VCS environment variables
# No VCD/VPD file
./simv-DefaultFPGAConfig -q +ntb_random_seed_automatic +dramsim \
+verbose +max-cycles=100000000 pk $TOP/riscv-tools/hello/hello.pk \
3>&1 1>&2 2>&3 | spike-dasm > hello.out && [ $PIPESTATUS -eq 0 ]
# VCD file
./simv-DefaultFPGAConfig-debug -q +ntb_random_seed_automatic \
+dramsim +verbose +vcdfile=hello.vcd +max-cycles=100000000 \
pk $TOP/riscv-tools/hello/hello.pk 3>&1 1>&2 2>&3 | \
spike-dasm > hello.out && [ $PIPESTATUS -eq 0 ]
# VPD file
./simv-DefaultFPGAConfig-debug -q +ntb_random_seed_automatic \
+dramsim +verbose +vcdplusfile=hello.vpd +max-cycles=100000000 \
pk $TOP/riscv-tools/hello/hello.pk 3>&1 1>&2 2>&3 | \
spike-dasm > hello.out && [ $PIPESTATUS -eq 0 ]
With a full Linux OS
Requirements: riscv-isa-sim
, riscv-fesvr
, riscv-gcc
, riscv-linux
, root.bin
# set up the RISCV environment variables
# set up the VCS environment variables
# boot the linux
./simv-DefaultFPGAConfig -q +ntb_random_seed_automatic +dramsim \
+verbose +max-cycles=1000000000 \
+disk=../riscv-tools/busybox-1.21.1/root.bin \
../riscv-tools/linux-3.14.13/vmlinux 3>&1 1>&2 2>&3 | \
spike-dasm > vmlinux.out && [ $PIPESTATUS -eq 0 ]
# in the booted linux
# /hello
The full Linux test can take HOURS and use up MULTIPLE GB space for log files.