// Your crsid your given name your family name // Year-month-day // // This program is free software, released under GNU GPL version 2 // tlights.v // Written by Frank Stajano based on code originally written by // Richard van der Hoff and George Taylor. // TUT: comments marked as 'TUT' in these instructor-supplied files // are there for tutorial purposes. Do copy the style of any other // comments, but not of these. If you base your work on this code, remove // the 'TUT' comments. // TUT: never exceed 79 characters per line in your source code (columns 0-78) // 1 2 3 4 5 6 7 // 3456789012345678901234567890123456789012345678901234567890123456789012345678 // Use 4 spaces (no tabs!) for each indent level. // The clock will be divided by 2^DIV `define DIV 25 // TUT: 'tlights' is the main module. Note that it has the same name as the // file to indicate that it is the top-level module in this file. Note also // that any ports of this module (here leds1, leds0 and ck) must appear in // the .acf file to be connected to actual pins of the FPGA. module tlights(led1, led0, ck); // Traffic lights simulator. // Cycle forever through green, amber, red in the usual sequence. // Use the three horizontal segments of a 7-segment LED display // to represent the three lights. output [7:0] led1, led0; input ck; wire enable; wire [2:0] lights; // Generate a slow clock clockdiv c(ck, slowCk); // The actual traffic lights state machine tlightscontrol t(slowCk, lights); // TUT: the above is bad practice, because the flip-flops in module 't' // are clocked from the derived signal 'slowCk'. You should only ever // clock flip-flops directly from the master clock signal coming into // the FPGA. // FIX THIS DESIGN so that it becomes properly synchronous. // seven segment layout: // |-0-| // 5 1 // |-6-| // 4 2 // |-3-| 7 // The leds are active-low, so we have to invert them. // TUT: we can assign to them bit by bit... assign led1[0] = !lights[0]; // Top assign led1[1] = 1; assign led1[2] = 1; assign led1[3] = !lights[2]; // Bottom assign led1[4] = 1; assign led1[5] = 1; assign led1[6] = !lights[1]; // Middle assign led1[7] = 1; // TUT: ...or all at once. assign led0 = ~(8'h00); // TUT: To get familiar with the syntax, try doing // the reverse. Assign values to 'led1' in one statement and // to 'led0' in eight separate statements. // TUT: note the difference between ~ and ! for negation. // Try exchanging them. endmodule // TUT: the following is evil. module clockdiv(fast, slow); // Clock divider. // Take a 'fast' clock waveform as input. Output a 'slow' clock // waveform whose frequency is 2^DIV times slower. input fast; output slow; reg [`DIV-1:0] counter; always @(posedge fast) begin counter <= counter+1; end assign slow = counter[`DIV-1]; endmodule `define RED 3'b001 `define AMBER 3'b010 `define GREEN 3'b100 module tlightscontrol(clock, lights); // Traffic lights controller. // Cycle through the usual sequence of "red-amber, green, amber, red". // Change state at every 'clock' edge. input clock; output [2:0] lights; reg [2:0] lights; // green, amber, red always @(posedge clock) begin case(lights) `RED: lights <= `RED | `AMBER; `RED | `AMBER: lights <= `GREEN; `GREEN: lights <= `AMBER; default: lights <= `RED; endcase end endmodule