2003-05-15 and 2003-05-22
University of Cambridge
Department of Engineering
Laboratory for Communication Engineering
|Week 1||Week 2|
[next to 'project matched what you hoped':] not sure yet
Some examples of commented code would have been useful since it is hard to know what is wanted!
Really struggled with syntax. Faults in software not known until demonstrator was consulted e.g. need to restart software if a module was removed to another file in the same directory or else the program would say it's missing.
Dr Stajano not helpful. Questions could be more specific and unambiguous.
Lectures too quick and brief
Maybe some syntax tutorial pages would've been useful
Quite hard, not knowing the syntax in Verilog. Software does not work properly if not restarted occasionally and unnecessary files are deleted.
[next to 'explanations: superficial / exhaustive':] optimum value in the time available, imo
Too much repetition about style of code, comments etc. A lot of time used up in saying all that and I feel we get the point.
Don't over-analyse the feedback!
compared to last week this was much harder to do in the time given. Since we couldn't prepare code in advance we wasted most of the demonstrator time fiddling with syntax rather than real problems.
Weekly tasks could be more explicit eg. terminating input with full stop description took a while to work out, maybe use an example alpha. beta. gamma . end
Some feedback on questions / more guidelines on how much is wanted for answers would be useful. 'Do it in style' was a bit vague on do's and don'ts, in relation to what was needed to get good marks. Weekly tasks could be on the web earlier so there is things to do at the weekend, otherwise it is hard to fit in 20 hrs between Monday and Thurs morning.
too easy to be careless when deciding 'what to implement'
[last smiley is 'very' sad] Much more difficult than fun
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