// tlights.v // // A verilog HDL file to simulate traffic lights // // rav21 24/08/99 // this is the main module - note that it has the same name as the // file (to indicate that it is the principal module in this file). module tlights( ledsA, ledsB, ck ); output [7:0] ledsA, ledsB; input ck; wire slow_clock; wire [2:0] lights; // divide the clock down so that we get a sensible rate clockdiv clockdivA( slow_clock, ck ); // the actual traffic lights state machine tlights_Mealy_simple tlightsA( lights,slow_clock ); // the leds are active-low, so we have to invert them. assign ledsA[0] = !lights[0]; // top assign ledsA[1] = 1; assign ledsA[2] = 1; assign ledsA[3] = !lights[2]; // bottom assign ledsA[4] = 1; assign ledsA[5] = 1; assign ledsA[6] = !lights[1]; // middle assign ledsA[7] = 1; assign ledsB = 8'hFF; endmodule // a clock divider // this defines the power of 2 by which we divide the clock. `define CLOCKDIV 25 module clockdiv( out, in ); output out; input in; reg [`CLOCKDIV-1:0] counter; always @(posedge in) begin counter <= counter+1; end assign out = counter[`CLOCKDIV-1]; endmodule // the traffic lights mealy machine - as seen in the notes module tlights_Mealy_simple( lights, clk ); output [2:0] lights; input clk; reg r,a,g; always @(posedge clk) begin r <= r^a; a <= !a; g <= r & a; end assign lights[0]=r; assign lights[1]=a; assign lights[2]=g; endmodule