CBG TOY BSV COMPILER VERSION 0.00 ALPHA 1st-Nov-2012 Top name 'cth-tiny/TinyTestBench.bsv' Args= /home/djg11/d320/hprls/bsvc/bsv.exe -o a.out -incdir=/home/djg11/d320/hprls/bsvc/smalltests:/home/djg11/d320/hprls/bsvc/camlib:/home/djg11/d320/hprls/bsvc/cth-tiny -cpp=disable -comb-assignment-delay=10 -vnl=dut.v -conerefine=disable cth-tiny/TinyTestBench.bsv -give-backtrace -elab-limit 10000 Compiled on 1/20/2013 6:26:10 PM struct BRAM.BRAMRequest Structure (total width 39) BRAM.BRAMRequest *-----------------+--------------------------------+-------+----------* | field | type | width | position | *-----------------+--------------------------------+-------+----------* | write | enum{...2} Bool | 1 | 38 | | responseOnWrite | enum{...2} Bool | 1 | 37 | | address | ^uint#(5,UInt#(Integer width)) | 5 | 32 | | datain | ^uint#(32,Int#(Integer width)) | 32 | 0 | *-----------------+--------------------------------+-------+----------* struct BRAM.BRAM_Configure Structure (total width 107) BRAM.BRAM_Configure *--------------------------+---------------------------------------+-------+----------* | field | type | width | position | *--------------------------+---------------------------------------+-------+----------* | memorySize | Integer | 32 | 75 | | latency | Integer | 32 | 43 | | loadFormat | { tagged union BRAM.LoadFormat} | 10 | 33 | | outFIFODepth | Integer | 32 | 1 | | allowWriteResponseBypass | enum{...2} Bool | 1 | 0 | *--------------------------+---------------------------------------+-------+----------* tunion BRAM.LoadFormat Tagged union (w=10,tw=2,a=3)(total width 10) BRAM.LoadFormat *--------+----------------------------+-----------* | field | type | tag value | *--------+----------------------------+-----------* | None | - | 0 | | Hex | Vector(-1, ^uint#(8,_Bit)) | 1 | | Binary | Vector(-1, ^uint#(8,_Bit)) | 2 | *--------+----------------------------+-----------* tunion Prelude.Maybe Tagged union (w=33,tw=1,a=2)(total width 33) Prelude.Maybe *---------+---------+-----------* | field | type | tag value | *---------+---------+-----------* | Invalid | - | 0 | | Valid | Integer | 1 | *---------+---------+-----------* tunion List.List Tagged union (w=1,tw=1,a=2)(total width 1) List.List *-------+------------------------------------------------------------------------+-----------* | field | type | tag value | *-------+------------------------------------------------------------------------+-----------* | Nil | - | 0 | | Cons | { struct List.List.ConsA1.} | 1 | *-------+------------------------------------------------------------------------+-----------* struct List.List.Cons Structure (recursive) List.List.Cons *-------+----------------------------+-------+----------* | field | type | width | position | *-------+----------------------------+-------+----------* | car | Vector(-1, ^uint#(8,_Bit)) | 8 | 0 | | cdr | Untied(List.List) | 0 | 0 | *-------+----------------------------+-------+----------* struct Prelude.Tuple2 Structure (total width 40) Prelude.Tuple2 *-------+----------------------------------------------+-------+----------* | field | type | width | position | *-------+----------------------------------------------+-------+----------* | tpl_1 | Vector(-1, ^uint#(8,_Bit)) | 8 | 32 | | tpl_2 | { tagged union TinyTypes.InstructionT} | 32 | 0 | *-------+----------------------------------------------+-------+----------* tunion TinyTypes.InstructionT Tagged union (w=32,tw=1,a=2)(total width 32) TinyTypes.InstructionT *-----------+--------------------------------------------------+-----------* | field | type | tag value | *-----------+--------------------------------------------------+-----------* | Normal | { struct TinyTypes.InstructionT.Normal} | 0 | | Immediate | { struct TinyTypes.InstructionT.Immediate} | 1 | *-----------+--------------------------------------------------+-----------* struct TinyTypes.InstructionT.Immediate Structure (total width 31) TinyTypes.InstructionT.Immediate *-------+---------------------------------+-------+----------* | field | type | width | position | *-------+---------------------------------+-------+----------* | rw | ^uint#(7,UInt#(Integer width)) | 7 | 24 | | imm | ^uint#(24,UInt#(Integer width)) | 24 | 0 | *-------+---------------------------------+-------+----------* struct TinyTypes.InstructionT.Normal Structure (total width 31) TinyTypes.InstructionT.Normal *-------+--------------------------------+-------+----------* | field | type | width | position | *-------+--------------------------------+-------+----------* | rw | ^uint#(7,UInt#(Integer width)) | 7 | 24 | | ra | ^uint#(7,UInt#(Integer width)) | 7 | 17 | | rb | ^uint#(7,UInt#(Integer width)) | 7 | 10 | | func | enum{...8} TinyTypes.FuncT | 3 | 7 | | shift | enum{...4} TinyTypes.ShiftT | 2 | 5 | | skip | enum{...4} TinyTypes.SkipT | 2 | 3 | | op | enum{...8} TinyTypes.OpcodeT | 3 | 0 | *-------+--------------------------------+-------+----------* /home/djg11/d320/hprls/bsvc/cth-tiny/TinyTypes.bsv: 16 typeDef enumeration SkipT Enumeration, arity 4 (total width 2).TinyTypes.SkipT *-----------+----------* | tag | encoding | *-----------+----------* | SkipNever | 0 | | SkipNeg | 1 | | SkipZero | 2 | | SkipInRdy | 3 | *-----------+----------* /home/djg11/d320/hprls/bsvc/cth-tiny/TinyTypes.bsv: 15 typeDef enumeration ShiftT Enumeration, arity 4 (total width 2).TinyTypes.ShiftT *------------+----------* | tag | encoding | *------------+----------* | ShiftNone | 0 | | ShiftRCY1 | 1 | | ShiftRCY8 | 2 | | ShiftRCY16 | 3 | *------------+----------* /home/djg11/d320/hprls/bsvc/cth-tiny/TinyTypes.bsv: 14 typeDef enumeration FuncT Enumeration, arity 8 (total width 3).TinyTypes.FuncT *-----------+----------* | tag | encoding | *-----------+----------* | FaADDb | 0 | | FaSUBb | 1 | | FINCb | 2 | | FDECb | 3 | | FaANDb | 4 | | FaORb | 5 | | FaXORb | 6 | | Freserved | 7 | *-----------+----------* /home/djg11/d320/hprls/bsvc/cth-tiny/TinyTypes.bsv: 13 typeDef enumeration OpcodeT Enumeration, arity 8 (total width 3).TinyTypes.OpcodeT *------------+----------* | tag | encoding | *------------+----------* | OpNormal | 0 | | OpStoreDM | 1 | | OpStoreIM | 2 | | OpOut | 3 | | OpLoadDM | 4 | | OpIn | 5 | | OpJump | 6 | | OpReserved | 7 | *------------+----------* End