PU17 Microprocessor

PU17 Processor Technical Specification.

This is a general purpose processor available as a Verilog synthesiable module. Its main reason for existing is for use in hardware/software codesign experiments, but it is useful enough for real purposes too.

The PU17 is an A16, D16 processor. The machine is LITTE ENDIAN so that coercions are simplified in C compiled code.

The PU17 has 16 bit registers and both byte and word (16bit) memory operations. There are 8 data registers and a PC. The data registers are mainly orthogonal, except that only R0-2 and R7 may be used for indexing and R6 is used for the link in a branch and link instruction. All instructions are either 2 or 4 bytes long. Subroutine link is through branch and link with R6 being the link register.

An assembler, C compiler and low-level monitor for this processor are all available in source code form: pu17cc.zip.

Archive:  pu17cc.zip
  Length     Date   Time    Name
 --------    ----   ----    ----
      230  04-10-99 15:51   README
    10821  12-03-98 18:18   aritharx.c
    37426  04-10-99 10:21   aspu17.c
     8185  03-22-99 19:30   ccc.c
    13178  04-08-99 10:08   ccchdr.h
    39546  04-10-99 11:41   compile.c
    22288  07-28-98 15:10   cpp.c
    12077  07-28-98 20:08   lex.c
      388  03-22-99 09:39   main.c
      824  04-10-99 15:49   makefile
     7835  04-07-99 10:26   mylinein.c
      490  04-09-99 08:35   mymachdep.h
    16462  04-10-99 18:21   mymon.c
    79149  04-10-99 18:21   obj
    34801  03-28-99 19:54   parser.c
    13287  04-08-99 22:49   prlibc.c
     1098  03-07-99 09:43   prstdio.h
     1360  04-10-99 15:00   pu17hdr.S
    49399  04-10-99 18:20   pugen.c
      131  12-03-98 17:56   spare
       24  12-03-98 12:28   target.h
     1896  04-02-99 17:16   targetpu.h
      135  04-10-99 11:33   test.c
 --------                   -------
   351030                   23 files


  • R0..R7 are 8 general purpose registers of 16 bits. R0-2 and R7 can be used as index registers R6 is the link register but can be used freely.
  • Flags register containing NZCV.
  • Program counter (PC) is 16 bits with bit 0 always zero.

    Addressing modes and instructions:

  • ALU operation on one register: LSR, LSL, ASL, ASR, left and right shifts by one bit.
  • One register and immediate 8 bit constant: ADD, SUB, ADDC, SUBC, TST, CMP.
  • Two registers: ADD, SUB, ADDC, SUBC, TST, CMP, MOV.
  • One register and 16 bit immediate constant: LOD, LODB.
  • One register and 16 bit absoluite address: LOD, LODB, STR, STRB.
  • Indexed load and stores where R0, R1, R2 or R7 is the index register and the offset is an even, twos complement value giving even values from -128 to 126: LOD, LODB, STR, STRB.
  • Branch on condition to absolute address or without condition to subroutine with link address put in R6: Jcc JSR
  • Branch on condition to relative offset (-256 or +254) : Bcc

    ALU operations

    ALU operations are encoded as follows: 1:add 2:sub 3:addc 4:subc 5:cmp 6:or 7:and 8:xor 9:asl/lsl 10:lsr 11:lsr 13:tst

    Branch conditions

    ALU operations update the NZCV flags in the same way as the 6800 processor and the branch conditions use the the same names.

    Conditional jump conditions are as follows. Condition 15 means unconditional branch and link in the absolute version and should not be used in the relative version. The conditions are encoded in a 4 bit cc field: 0:EQ 1:NE 3:LT 3:GE 4:GT 5:LE 6:C 7:NC 8:V 9:NV 10:ALWAYS 11:HI 12:LS 13:MI 14:PL 15:SUB

    Load and Store Multiple

    R7 is the index register used for load and store multiple and hence is normally used as the stack pointer. Registers are stored or loaded from the address pointed to by R7, which must be even, upwards. R7 is not changed by LDM/STM unless it is a destination for LDM.

    The current calling method generated by the C compiler does not use LDM/STM. This will be used in the enhanced version.


    Reset is to address 0 with other registers unchanged.

    No interrupts at the moment.

    Instruction Set Summary Table

    The top four bits of an instruction essentially contain the opcode. Read the source for the assembler or Verilog for details.

    0-7     0xxx.   R3DEST, ALU4,  IMMED8	   		: Imm 8 bit 
                         7,    3,  14-10, 2-0
    8-B 	10xx.	 BYTEF, STOREF,   IDXR2, REG3,  IDX7,   : Indexed load/store
                       13,      12,   10,    7,     0       : 
    C	1100.	COND4, OFFSET8				: Relative branches
                        8        0                          :
    D0	1101.00	R3DEST, ALU4, R3SRC	   		: ALU reg,reg ops
                         7     3      0                     :
    D4	1101.01	REG3, BYTEF1,  STOREF, ABS16		: Abs16 load/store
                       7       6        5,  next            : (4 bytes) 
    D8	1101.10 COND4, ABS16				: Absolute jmp jsr   
                        2,                                  : (4 bytes)  
    DC      1101.11 RLIST8 STOREF                           : Load/store multiple
                         2,     1                           : 
    F0	1111.00 REG3 	LinkF				: Branch indirect 
    	           7,       0                           : bx, bxl
    F4      1111.01 REG3, Immed16				: Load immediate 
                       7                                    : (4 bytes)

    The return instruction 'ret' is branch indirect on R6 'bx r6'.

    The assembler supports putting a jcc for a bcc, where the distance is too far for a relative offset.

    The offset in relative jumps is the offset from the instruction divided by 2.

    C linkage.

    R7 is the base register for C compiled code. Args 0 and 1 are passed in registers 0 and 1 with the result being in R0 (or R0low, R1high if a long (32 bits)). R2 on entry is the new R7, with the stack working downwards.

    Source Code

    The Verilog source code for the PU17 plus some uarts and other bits is in this zip pu17.zip.

    C Model

    A machine-generated C Model of the PU17 is here pu17c.c,


    The following file is an assembly listing of the mymon monitor compiled for PU17.
  • (C) 1998 Mixerton ST/Univ Cambridge.