University of Cambridge, Computer Laboratory

Hardware Design Exercise for Part II General 2006/07

Please answer all parts of this exercise in the form of a short report and deliver to Ms F Billingsley at the Gates Building before noon on Friday 26th January 2007. Candidates will be interviewed about their solution and asked to resubmit if they cannot explain it or it contains major errors. The work must be completed to a high standard using word processing equipment, although circuits can be hand drawn.

Candidates are encouraged to seek the assistance of their Supervisor to complete this exercise where they feel it necessary. The date of submission is set one week after the start of term for this purpose.

All of the logic in the system designed should be fully synchronous, meaning there is just one clock module that connects directly to the clock input of every flip-flop. Note: it is often helpful to decompose larger circuits into smaller sections that can be instantiated more than once. You are encouraged to do this.

In all previous years, a large number of people have ignored the directive to produce a synchronous design so it seems reasonable to repeat this directive here, even though repeating it does not seem to have had much effect in the past. All of the logic in the system designed should be fully synchronous, meaning that there is just one clock module that connects absolutely directly to the clock input of every flip-flop.

Part a, Clock enable flip-flop

Give the circuit for a device that is like a D-type flip flop and which internally uses a D-type flip-flop but which has an additional input that is a clock enable. When the clock enable is low, the device does not take any notice of its data input and when the enable is high it behaves like a normal D-type. (NB: this device is just an FSM and it will not change state as a result of an edge on its enable input.) Give also a schematic symbol of your choosing for this device. You should use this part where appropriate in the sequel. (Also, please take note of the repeated instruction above, which means that simply ANDing the clock with the clock enable is not acceptable because it can cause glitches and breaks the repeated rule.)

Part b, Pseudo Random Number Generator

Design the circuit for a pseudo random number generator made of 15 clock enable flip-flops. These should be wired as a shift register with the overall input of the shift register fed from the XOR of the last two outputs. The generator has 2 outputs, taken from bits 2 and 7. It has one input (apart from the clock), which is its clock enable. The core of circuit is shown here, but the required generator should also have a gate that spots the degenerate state of all zeros and causes the module to move out of it. Explain briefly what the circuit does (a full state listing is not required). Give also a schematic symbol of your choosing for this device.

Part c, Programmable Divider

Give the circuit of a programmable divider that accepts a twelve-bit number on 12 inputs and a clock and generates an output that is asserted for one clock cycle every N clock cycles where N is the current value of the 12 bit number. Use ripple carry. Give also a schematic symbol of your choosing for this device. Note that a twelve-bit number is not the same thing as a four bit number in the range 0 to 11. The most simple solution to this section loads the twelve-bit number into a down counter each time it reaches zero.

Part d, Push Button Input Unit

Give the state diagram and internal circuit for a four-button input unit. This unit has a clock input and a two-bit binary output. It contains four push-to-make buttons. At all times, the output encodes in binary the last selection the user made when he/she pressed one of the buttons. Give also a schematic symbol of your choosing for this device.

Part e, Unary up/down counter and LED display

Give the state diagram for a synchronous FSM that accepts a clock and a pair of inputs called up and down. The output is 12 wires that hold a 12 bit unary number, meaning that exactly one output bit is asserted at any one time. Each output is to be connected to an LED driver circuit and so only one LED will be on at a time. When clocked, if the up wire is asserted, the lit LED will move to the left one position, provided it is not already at the left. If the down wire is asserted, it will move to the right one position, if it is not already at the right-hand end. If neither input is asserted the currently lit LED is unchanged. The internal circuit of this part is not required, but give a schematic logic symbol of your choosing for the part as a whole. I repeat, the circuit is not required.

Part f, Electronic Amusement

An electronic game consists of four LEDs and four push buttons. There are also further LEDs to indicate in unary the score which is the current performance of the player. Initially, the score starts at its lowest with the right-hand LED on. The game proceeds in rounds and the initial frequency of rounds is once every 2 seconds, but this speeds up as the player improves his score, thus making it increasingly harder to achieve higher scores.

Always one of the four LEDs is on and this may change according to a psuedo random pattern to another of the four LEDs at the end of each round. The player must press the button corresponding to the lit LED before the end of the round. If he has pressed the correct button, the score moves to the left by one and if he does not, the score goes back to the right by one. As the score moves to the left, the time delay for a new round decreases and so the rate of the rounds increases.

An implementation of the game uses the four modules designed above in parts b to e. A full state diagram for the game hardware would therefore by highly complex, but when decomposed using the modules you have designed, a very simple view is possible. Show the wiring necessary to interconnect the modules to form the game. If you use additional flip-flops, beyond those used in the four modules, to form a controller for the game, include these in the wiring diagram and also give a state diagram for the controller.

Thank you. DJG.