Serial Transmitter Example

Here is a very simple example of CTOV capabilities. This example uses no arrays and has no inputs and a single, one bit wide output. It is an example where the designer needs precise control over clock cycle deployment.

In this example, we generate a pair of control words consisting of 16 bit numbers sent most-significant bit first. The msb of the number is always zero, making a start bit, and we force 32 stop bits between calls.

The following are the command lines placed as part of a makefile to create this example:

serialw:cxlibc/c2mllibc.pt tests/toscachip.c
	ctov -o tests/serialw.v -oroot SERIALW  -iroot serialw \
		   -read tests/toscachip 
	cv2.100 tests/serialw.v -vnl -o tests/serialw.vnl -root SERIALW
The CTOV command is run to produce a file called `serialw.v' containing a Verilog module called `SERIALW' which has been generated from the C routine called `serialw' in the file `toscachip.c'. Then the cv2.100 command is used to compile the Verilog to a netlist in the file `serialw.vnl'.

Here is the relevant C source code found in part of the file toscachip.c:

/* 
 * Code to set the control reg in the ST TOSCA ADSL front end
 */

#include <cxctypes.h>
/* This code was compiled into 4006 Xilinx FPGA using CTOV compiler */

/*
 * Send a 16 bit quantity to the tosca control register, msb first.
 * Bit 15 of d is always zero and acts as a start bit
 */
void sendword(u16 d, u1 *outptr)
{
  volatile u16 i;
  *outptr = 1;  /* Send 32 stop bits first */
  for (i=0;i<32; i++) cx_barrier();
  for (i=0;i<16;i++)
    {
      *outptr = ((d>>15) & 1);
      d = d << 1;
      cx_barrier();
    }
  *outptr = 1;
  cx_barrier();
  return;
}


/*
 * Routine to write to the tosca control register.
 */
void serialw(u1 *ctrlout)
{
  sendword(0x252, ctrlout);
  /* Comment out second call to make demo shorter to read */
  /* sendword(0x624, ctrlout); */
}

A notable feature of the C source file is the use of `u16' to denote an unsigned integer of size 16 bits. `u1' is also used. A full set of such definitions up to 64 bits is present in the `cxctypes.h' header file. These are set up using conditional preprocessing from the C macroprocessor such that CTOV can read the exact width in bits, whereas a normal C compiler, such as GCC, will use an appropriate sized C value, which would be `unsigned short' for a `u16'. If the source code instead uses the standard C sizes, by rounding up the desired size to the next highest available, then the registers generated by CTOV may be larger than required, but even if this is the case, the spare top bits will often be trimmed automatically in post processing (for instance, it if is determined that they will always be zero or other constant or if their outputs are not referenced).

We see that the output from our circuit is represented by call by reference. In CTOV, function calls are allowed to return values as in standard C, but the value returned from the top level routine is ignored, so all outputs must use call by reference. (An exception to this is where outputs are to arrays which are mapped to separately-compiled or `off chip' RAMs.)

A notable feature are the calls to `cx_barrier()'. Out example os of the class where the output has no handshake and must be timed exactly in clock cycles from a hidden clock. Each `cx_barrier()' call consumes exactly one clock cycle. Note that each WHILE loop has a a barrier in its body and that the loop variable is declared `volatile'. We will discuss this in a future version of this manual/example. Off-the-shelf sections of C or designs which do not require tight control over clock cycle deployment do not have to be augmented with calls to the barrier routines. When C code designed for CTOV containing barriers is to be compiled by a normal C compiler, then the barrier routine can be replaced with a null or possibly a link to a reschedule offer in a threads library.

Here is the Verilog generated by CTOV in this compilation:

/* /homes/djg/d300/cv3/cv3core ctov -o tests/serialw.v -oroot SERIALW -iroot serialw -read tests/toscachip  */
/* User=/home/djg  */

module SERIALW (ctrlout, clk, cx_reset);
  supply0 LGND; supply1 LVCC;
  output ctrlout;
  input clk;
  input cx_reset;
  wire cxpin_1009;
  wire cxpin_1008;
  wire cxpin_1007;
  wire cxpin_1006;
  wire cxpin_1005;
  wire cxpin_1004;
  wire cxpin_1003;
  reg [15:0] i110;
  reg outptr109;
  reg [15:0] d108;
  reg [15:0] i;
  reg outptr;
  reg [15:0] d;
  reg [7:0] ctov__zeroflag;
  reg [31:0] chold_1002;
  wire ac_ac_ttfbrk104LLLLL;
  wire ac_ac_ttftop106LtLLLL;
  wire ac_ac_ttftop103Lt;
  wire ac_ac_node_startLLLLLLLLLt;
  reg [2:0] tt_statereg;
  wire ac_alpha_zero;


 always  @(posedge clk)  begin   chold_1002 <= ctrlout;

  tt_statereg <= (cx_reset) ? 0:(~(1+i<16) && ac_ac_ttftop106LtLLLL) ? 4:((~(1+i<32) && ac_ac_node_startLLLLLLLLLt) || ((~(1+i<32) && ac_ac_ttftop103Lt) || (1+i<16 && ac_ac_ttftop106LtLLLL))) ? 3:((1+i<32 && ac_ac_node_startLLLLLLLLLt) || (1+i<32 && ac_ac_ttftop103Lt)) ? 2:(ac_alpha_zero) ? 1:(0) ? 0:tt_statereg;

  outptr <= (cxpin_1003) ? ctrlout:outptr;

  d <= (cxpin_1006 || (cxpin_1005 || cxpin_1004)) ? d<<1:(cxpin_1003) ? 594:d;

  i <= (cxpin_1007) ? 1+i:(cxpin_1006 || cxpin_1005) ? 0:(cxpin_1004 || (cxpin_1009 || cxpin_1008)) ? 1+i:(cxpin_1003) ? 0:i;

  end
  assign ac_ac_ttfbrk104LLLLL  = 4==tt_statereg;
  assign ac_ac_ttftop106LtLLLL  = 3==tt_statereg;
  assign ac_ac_ttftop103Lt  = 2==tt_statereg;
  assign ac_ac_node_startLLLLLLLLLt  = 1==tt_statereg;
  assign ac_alpha_zero  = 0==tt_statereg;
  assign cxpin_1009  = 1+i<32 && ac_ac_node_startLLLLLLLLLt;
  assign cxpin_1008  = 1+i<32 && ac_ac_ttftop103Lt;
  assign cxpin_1007  = ~(1+i<16) && ac_ac_ttftop106LtLLLL;
  assign cxpin_1006  = ~(1+i<32) && ac_ac_node_startLLLLLLLLLt;
  assign cxpin_1005  = ~(1+i<32) && ac_ac_ttftop103Lt;
  assign cxpin_1004  = 1+i<16 && ac_ac_ttftop106LtLLLL;
  assign cxpin_1003  = ac_alpha_zero;
  assign ctrlout  = (cxpin_1007) ? 1:(cxpin_1006 || (cxpin_1005 || cxpin_1004)) ? d>>15 & 1:(cxpin_1003) ? 1:chold_1002;

endmodule

The Verilog is not very easy to read. Output optimisation has been turned off in this example, but most of the optimisations that CTOV would do will actually be done in post-processing tools anyway.

We note that the variable `tt_statereg' has been generated. This variable acts like a program counter. The report file generated by CTOV gives a rough mapping from the values of statereg to line numbers in the C source code.

A binary coding for statereg is used by default, but the command line flag `-onehotf' can be used to change to a one-hot coding for the sequencer states if this is found more convenient in post-processing tools.

The compiler has generated a number of intermediate signals driven by continuous assignment. These signals have names which are textually related to the structure of the source file in an obscure way. Each contains a unique number and these increase with progress of the nominal thread through the compilation.

The Verilog module has two further connections beyond those specified in the source design, these are the clock input and the active high synchronous reset.

In our example. the input code section is not an infinite loop, although many practical applications of CTOV will use an infinite loop. Therefore the state machine will run once after reset is deasserted and then stop.

Here is the netlist generated by cv2.100 from the example.

/* cv2.100 tests/serialw.v -vnl -o tests/serialw.vnl -root SERIALW  */
/* User=/home/djg  */
/* output from CBG CV2/100 CBG cv2 V100.2 alpha. CBG/TT CVA EDA CORE (Core release 1.3m regression). */


module SERIALW (ctrlout, clk, cx_reset);
  supply0 LGND; supply1 LVCC;
  output ctrlout;
  input clk;
  input cx_reset;
  wire /* lid */ I387;
  wire /* lid */ g386;
  wire /* lid */ I385;
  wire /* lid */ I384;
  wire /* lid */ g383;
  wire /* lid */ g382;
  wire /* lid */ I381;
  wire /* lid */ g380;
  wire /* lid */ g379;
  wire /* lid */ I378;
  wire /* lid */ I377;
  wire /* lid */ g376;
  wire /* lid */ g375;
  wire /* lid */ I374;
  wire /* lid */ I373;
  wire /* lid */ g372;
  wire /* lid */ g371;
  wire /* lid */ g370;
  wire /* lid */ mq369;
  wire /* lid */ g368;
  wire /* lid */ mq366;
  wire /* lid */ g365;
  wire /* lid */ mq364;
  wire /* lid */ g363;
  wire /* lid */ mq361;
  wire /* lid */ g360;
  wire /* lid */ mq359;
  wire /* lid */ g358;
  wire /* lid */ mq356;
  wire /* lid */ g355;
  wire /* lid */ mq354;
  wire /* lid */ g353;
  wire /* lid */ mq351;
  wire /* lid */ g350;
  wire /* lid */ mq349;
  wire /* lid */ g348;
  wire /* lid */ mq346;
  wire /* lid */ g345;
  wire /* lid */ mq344;
  wire /* lid */ g343;
  wire /* lid */ mq341;
  wire /* lid */ g340;
  wire /* lid */ mq339;
  wire /* lid */ g338;
  wire /* lid */ mq336;
  wire /* lid */ g335;
  wire /* lid */ mq334;
  wire /* lid */ g333;
  wire /* lid */ mq331;
  wire /* lid */ g330;
  wire /* lid */ mq329;
  wire /* lid */ g328;
  wire /* lid */ mq326;
  wire /* lid */ g325;
  wire /* lid */ mq324;
  wire /* lid */ g323;
  wire /* lid */ mq321;
  wire /* lid */ g320;
  wire /* lid */ mq319;
  wire /* lid */ g318;
  wire /* lid */ mq316;
  wire /* lid */ g315;
  wire /* lid */ mq314;
  wire /* lid */ g313;
  wire /* lid */ mq311;
  wire /* lid */ g310;
  wire /* lid */ mq309;
  wire /* lid */ g308;
  wire /* lid */ mq306;
  wire /* lid */ g305;
  wire /* lid */ mq304;
  wire /* lid */ g303;
  wire /* lid */ g302;
  wire /* lid */ mq300;
  wire /* lid */ g299;
  wire /* lid */ mq298;
  wire /* lid */ g297;
  wire /* lid */ g296;
  wire /* lid */ mq294;
  wire /* lid */ g293;
  wire /* lid */ mq292;
  wire /* lid */ g291;
  wire /* lid */ g290;
  wire /* lid */ g288;
  wire /* lid */ I287;
  wire /* lid */ mq286;
  wire /* lid */ g285;
  wire /* lid */ mq284;
  wire /* lid */ g283;
  wire /* lid */ g282;
  wire /* lid */ g281;
  wire /* lid */ I280;
  wire /* lid */ g279;
  wire /* lid */ I278;
  wire /* lid */ mq276;
  wire /* lid */ g275;
  wire /* lid */ mq273;
  wire /* lid */ g272;
  wire /* lid */ mq270;
  wire /* lid */ g269;
  wire /* lid */ mq267;
  wire /* lid */ g266;
  wire /* lid */ mq264;
  wire /* lid */ g263;
  wire /* lid */ mq261;
  wire /* lid */ g260;
  wire /* lid */ mq258;
  wire /* lid */ g257;
  wire /* lid */ mq255;
  wire /* lid */ g254;
  wire /* lid */ mq252;
  wire /* lid */ g251;
  wire /* lid */ mq249;
  wire /* lid */ g248;
  wire /* lid */ mq246;
  wire /* lid */ g245;
  wire /* lid */ mq243;
  wire /* lid */ g242;
  wire /* lid */ mq240;
  wire /* lid */ g239;
  wire /* lid */ mq237;
  wire /* lid */ g236;
  wire /* lid */ g234;
  wire /* lid */ mq233;
  wire /* lid */ g232;
  wire /* lid */ g230;
  wire /* lid */ g229;
  wire /* lid */ I228;
  wire /* lid */ I227;
  wire /* lid */ g226;
  wire /* lid */ g225;
  wire /* lid */ g223;
  wire /* lid */ g222;
  wire /* lid */ g221;
  wire /* lid */ g220;
  wire /* lid */ g219;
  wire /* lid */ I218;
  wire /* lid */ g216;
  wire /* lid */ g215;
  wire /* lid */ g214;
  wire /* lid */ g213;
  wire /* lid */ g212;
  wire /* lid */ I211;
  wire /* lid */ g209;
  wire /* lid */ g208;
  wire /* lid */ g207;
  wire /* lid */ g206;
  wire /* lid */ g205;
  wire /* lid */ I204;
  wire /* lid */ g203;
  wire /* lid */ g202;
  wire /* lid */ g201;
  wire /* lid */ g200;
  wire /* lid */ g199;
  wire /* lid */ g198;
  wire /* lid */ g197;
  wire /* lid */ g196;
  wire /* lid */ I195;
  wire /* lid */ g194;
  wire /* lid */ g193;
  wire /* lid */ g192;
  wire /* lid */ g191;
  wire /* lid */ g190;
  wire /* lid */ g189;
  wire /* lid */ g188;
  wire /* lid */ g187;
  wire /* lid */ g186;
  wire /* lid */ g185;
  wire /* lid */ I184;
  wire /* lid */ g183;
  wire /* lid */ I182;
  wire /* lid */ g181;
  wire /* lid */ g180;
  wire /* lid */ g179;
  wire /* lid */ g178;
  wire /* lid */ g177;
  wire /* lid */ g176;
  wire /* lid */ g175;
  wire /* lid */ g174;
  wire /* lid */ g173;
  wire /* lid */ g172;
  wire /* lid */ g171;
  wire /* lid */ I170;
  wire /* lid */ g169;
  wire /* lid */ I168;
  wire /* lid */ g167;
  wire /* lid */ I166;
  wire /* lid */ g165;
  wire /* lid */ I164;
  wire /* lid */ g163;
  wire /* lid */ I162;
  wire /* lid */ g161;
  wire /* lid */ I160;
  wire /* lid */ g159;
  wire /* lid */ I158;
  wire /* lid */ g157;
  wire /* lid */ I156;
  wire /* lid */ g155;
  wire /* lid */ I154;
  wire /* lid */ g153;
  wire /* lid */ I152;
  wire /* lid */ g151;
  wire /* lid */ I150;
  wire /* lid */ g149;
  wire /* lid */ I148;
  wire /* lid */ g147;
  wire /* lid */ g146;
  wire /* lid */ g145;
  wire /* lid */ g144;
  wire /* lid */ g143;
  wire /* lid */ g142;
  wire /* lid */ g141;
  wire /* lid */ g140;
  wire /* lid */ g139;
  wire /* lid */ g138;
  wire /* lid */ g137;
  wire /* lid */ g136;
  wire /* lid */ g135;
  wire /* lid */ g134;
  wire /* lid */ g133;
  wire /* lid */ I132;
  wire ac_alpha_zero;
  reg [2:0] tt_statereg;
  wire ac_ac_node_startLLLLLLLLLt;
  wire ac_ac_ttftop103Lt;
  wire ac_ac_ttftop106LtLLLL;
  wire ac_ac_ttfbrk104LLLLL;
  reg [31:0] chold_1002;
  reg [7:0] ctov__zeroflag;
  reg [15:0] d;
  reg outptr;
  reg [15:0] i;
  reg [15:0] d108;
  reg outptr109;
  reg [15:0] i110;
  wire cxpin_1003;
  wire cxpin_1004;
  wire cxpin_1005;
  wire cxpin_1006;
  wire cxpin_1007;
  wire cxpin_1008;
  wire cxpin_1009;
  BUF  ac_ac_ttfbrk104LLLLL(ac_ac_ttfbrk104LLLLL, I387);
  INV  I387(I387, g386);
  OR2  g386(g386, I385, g371);
  INV  I385(I385, tt_statereg[2]);
  BUF  ac_ac_ttftop106LtLLLL(ac_ac_ttftop106LtLLLL, I384);
  INV  I384(I384, g383);
  OR2  g383(g383, g382, tt_statereg[2]);
  OR2  g382(g382, I378, I374);
  BUF  ac_ac_ttftop103Lt(ac_ac_ttftop103Lt, I381);
  INV  I381(I381, g380);
  OR2  g380(g380, g379, tt_statereg[2]);
  OR2  g379(g379, I378, tt_statereg[0]);
  INV  I378(I378, tt_statereg[1]);
  BUF  ac_ac_node_startLLLLLLLLLt(ac_ac_node_startLLLLLLLLLt, I377);
  INV  I377(I377, g376);
  OR2  g376(g376, g375, tt_statereg[2]);
  OR2  g375(g375, I374, tt_statereg[1]);
  INV  I374(I374, tt_statereg[0]);
  BUF  ac_alpha_zero(ac_alpha_zero, I373);
  INV  I373(I373, g372);
  OR2  g372(g372, g371, tt_statereg[2]);
  OR2  g371(g371, tt_statereg[0], tt_statereg[1]);
  BUF  cxpin_1009(cxpin_1009, g201);
  BUF  cxpin_1008(cxpin_1008, g202);
  BUF  cxpin_1007(cxpin_1007, g183);
  BUF  cxpin_1006(cxpin_1006, g196);
  BUF  cxpin_1005(cxpin_1005, g197);
  BUF  cxpin_1004(cxpin_1004, g198);
  BUF  cxpin_1003(cxpin_1003, ac_alpha_zero);
  BUF  ctrlout(ctrlout, g370);
  OR2  g370(g370, mq369, cxpin_1007);
  MUX2  mq369(mq369, g226, d[15], g368);
  OR2  g368(g368, chold_1002[0], cxpin_1003);
  DFF  i15i367(i[15], mq366, clk, g288, LGND, LGND);
  MUX2  mq366(mq366, cxpin_1007, g147, g365);
  AND2  g365(g365, mq364, I280);
  MUX2  mq364(mq364, g282, g147, g363);
  AND2  g363(g363, I228, i[15]);
  DFF  i14i362(i[14], mq361, clk, g288, LGND, LGND);
  MUX2  mq361(mq361, cxpin_1007, g149, g360);
  AND2  g360(g360, mq359, I280);
  MUX2  mq359(mq359, g282, g149, g358);
  AND2  g358(g358, I228, i[14]);
  DFF  i13i357(i[13], mq356, clk, g288, LGND, LGND);
  MUX2  mq356(mq356, cxpin_1007, g151, g355);
  AND2  g355(g355, mq354, I280);
  MUX2  mq354(mq354, g282, g151, g353);
  AND2  g353(g353, I228, i[13]);
  DFF  i12i352(i[12], mq351, clk, g288, LGND, LGND);
  MUX2  mq351(mq351, cxpin_1007, g153, g350);
  AND2  g350(g350, mq349, I280);
  MUX2  mq349(mq349, g282, g153, g348);
  AND2  g348(g348, I228, i[12]);
  DFF  i11i347(i[11], mq346, clk, g288, LGND, LGND);
  MUX2  mq346(mq346, cxpin_1007, g155, g345);
  AND2  g345(g345, mq344, I280);
  MUX2  mq344(mq344, g282, g155, g343);
  AND2  g343(g343, I228, i[11]);
  DFF  i10i342(i[10], mq341, clk, g288, LGND, LGND);
  MUX2  mq341(mq341, cxpin_1007, g157, g340);
  AND2  g340(g340, mq339, I280);
  MUX2  mq339(mq339, g282, g157, g338);
  AND2  g338(g338, I228, i[10]);
  DFF  i9i337(i[9], mq336, clk, g288, LGND, LGND);
  MUX2  mq336(mq336, cxpin_1007, g159, g335);
  AND2  g335(g335, mq334, I280);
  MUX2  mq334(mq334, g282, g159, g333);
  AND2  g333(g333, I228, i[9]);
  DFF  i8i332(i[8], mq331, clk, g288, LGND, LGND);
  MUX2  mq331(mq331, cxpin_1007, g161, g330);
  AND2  g330(g330, mq329, I280);
  MUX2  mq329(mq329, g282, g161, g328);
  AND2  g328(g328, I228, i[8]);
  DFF  i7i327(i[7], mq326, clk, g288, LGND, LGND);
  MUX2  mq326(mq326, cxpin_1007, g163, g325);
  AND2  g325(g325, mq324, I280);
  MUX2  mq324(mq324, g282, g163, g323);
  AND2  g323(g323, I228, i[7]);
  DFF  i6i322(i[6], mq321, clk, g288, LGND, LGND);
  MUX2  mq321(mq321, cxpin_1007, g165, g320);
  AND2  g320(g320, mq319, I280);
  MUX2  mq319(mq319, g282, g165, g318);
  AND2  g318(g318, I228, i[6]);
  DFF  i5i317(i[5], mq316, clk, g288, LGND, LGND);
  MUX2  mq316(mq316, cxpin_1007, g167, g315);
  AND2  g315(g315, mq314, I280);
  MUX2  mq314(mq314, g282, g167, g313);
  AND2  g313(g313, I228, i[5]);
  DFF  i4i312(i[4], mq311, clk, g288, LGND, LGND);
  MUX2  mq311(mq311, cxpin_1007, g169, g310);
  AND2  g310(g310, mq309, I280);
  MUX2  mq309(mq309, g282, g169, g308);
  AND2  g308(g308, I228, i[4]);
  DFF  i3i307(i[3], mq306, clk, g288, LGND, LGND);
  MUX2  mq306(mq306, cxpin_1007, g302, g305);
  AND2  g305(g305, mq304, I280);
  MUX2  mq304(mq304, g282, g302, g303);
  AND2  g303(g303, I228, i[3]);
  XOR2  g302(g302, g134, i[3]);
  DFF  i2i301(i[2], mq300, clk, g288, LGND, LGND);
  MUX2  mq300(mq300, cxpin_1007, g296, g299);
  AND2  g299(g299, mq298, I280);
  MUX2  mq298(mq298, g282, g296, g297);
  AND2  g297(g297, I228, i[2]);
  XOR2  g296(g296, g133, i[2]);
  DFF  i1i295(i[1], mq294, clk, g288, LGND, LGND);
  MUX2  mq294(mq294, cxpin_1007, g290, g293);
  AND2  g293(g293, mq292, I280);
  MUX2  mq292(mq292, g282, g290, g291);
  AND2  g291(g291, I228, i[1]);
  XOR2  g290(g290, i[1], i[0]);
  DFF  i0i289(i[0], mq286, clk, g288, LGND, LGND);
  OR2  g288(g288, I287, cxpin_1007);
  INV  I287(I287, cxpin_1007);
  MUX2  mq286(mq286, cxpin_1007, I278, g285);
  AND2  g285(g285, mq284, I280);
  MUX2  mq284(mq284, g282, I278, g283);
  AND2  g283(g283, I228, i[0]);
  OR2  g282(g282, g281, cxpin_1004);
  OR2  g281(g281, cxpin_1009, cxpin_1008);
  INV  I280(I280, g279);
  OR2  g279(g279, cxpin_1006, cxpin_1005);
  INV  I278(I278, i[0]);
  DFF  i15d277(d[15], mq276, clk, g234, LGND, LGND);
  MUX2  mq276(mq276, g226, d[14], g275);
  AND2  g275(g275, I228, d[15]);
  DFF  i14d274(d[14], mq273, clk, g234, LGND, LGND);
  MUX2  mq273(mq273, g226, d[13], g272);
  AND2  g272(g272, I228, d[14]);
  DFF  i13d271(d[13], mq270, clk, g234, LGND, LGND);
  MUX2  mq270(mq270, g226, d[12], g269);
  AND2  g269(g269, I228, d[13]);
  DFF  i12d268(d[12], mq267, clk, g234, LGND, LGND);
  MUX2  mq267(mq267, g226, d[11], g266);
  AND2  g266(g266, I228, d[12]);
  DFF  i11d265(d[11], mq264, clk, g234, LGND, LGND);
  MUX2  mq264(mq264, g226, d[10], g263);
  AND2  g263(g263, I228, d[11]);
  DFF  i10d262(d[10], mq261, clk, g234, LGND, LGND);
  MUX2  mq261(mq261, g226, d[9], g260);
  AND2  g260(g260, I228, d[10]);
  DFF  i9d259(d[9], mq258, clk, g234, LGND, LGND);
  MUX2  mq258(mq258, g226, d[8], g257);
  OR2  g257(g257, d[9], cxpin_1003);
  DFF  i8d256(d[8], mq255, clk, g234, LGND, LGND);
  MUX2  mq255(mq255, g226, d[7], g254);
  AND2  g254(g254, I228, d[8]);
  DFF  i7d253(d[7], mq252, clk, g234, LGND, LGND);
  MUX2  mq252(mq252, g226, d[6], g251);
  AND2  g251(g251, I228, d[7]);
  DFF  i6d250(d[6], mq249, clk, g234, LGND, LGND);
  MUX2  mq249(mq249, g226, d[5], g248);
  OR2  g248(g248, d[6], cxpin_1003);
  DFF  i5d247(d[5], mq246, clk, g234, LGND, LGND);
  MUX2  mq246(mq246, g226, d[4], g245);
  AND2  g245(g245, I228, d[5]);
  DFF  i4d244(d[4], mq243, clk, g234, LGND, LGND);
  MUX2  mq243(mq243, g226, d[3], g242);
  OR2  g242(g242, d[4], cxpin_1003);
  DFF  i3d241(d[3], mq240, clk, g234, LGND, LGND);
  MUX2  mq240(mq240, g226, d[2], g239);
  AND2  g239(g239, I228, d[3]);
  DFF  i2d238(d[2], mq237, clk, g234, LGND, LGND);
  MUX2  mq237(mq237, g226, d[1], g236);
  AND2  g236(g236, I228, d[2]);
  DFF  i1d235(d[1], mq233, clk, g234, LGND, LGND);
  OR2  g234(g234, I227, g226);
  MUX2  mq233(mq233, g226, d[0], g232);
  OR2  g232(g232, d[1], cxpin_1003);
  DFF  i0d231(d[0], g230, clk, LVCC, LGND, LGND);
  AND2  g230(g230, g229, I227);
  AND2  g229(g229, I228, d[0]);
  INV  I228(I228, cxpin_1003);
  INV  I227(I227, g226);
  OR2  g226(g226, g225, cxpin_1006);
  OR2  g225(g225, cxpin_1005, cxpin_1004);
  DFF  outptr(outptr, ctrlout, clk, cxpin_1003, LGND, LGND);
  DFF  i2tt_statereg224(tt_statereg[2], g223, clk, LVCC, LGND, LGND);
  AND2  g223(g223, I132, g222);
  OR2  g222(g222, g183, g221);
  AND2  g221(g221, I218, g220);
  AND2  g220(g220, g219, I204);
  AND2  g219(g219, I211, tt_statereg[2]);
  INV  I218(I218, g200);
  DFF  i1tt_statereg217(tt_statereg[1], g216, clk, LVCC, LGND, LGND);
  AND2  g216(g216, g215, I132);
  AND2  g215(g215, I184, g214);
  OR2  g214(g214, g213, g200);
  OR2  g213(g213, g203, g212);
  AND2  g212(g212, I211, tt_statereg[1]);
  INV  I211(I211, ac_alpha_zero);
  DFF  i0tt_statereg210(tt_statereg[0], g209, clk, LVCC, LGND, LGND);
  AND2  g209(g209, g208, I132);
  AND2  g208(g208, g207, I184);
  OR2  g207(g207, g206, g200);
  AND2  g206(g206, g205, I204);
  OR2  g205(g205, ac_alpha_zero, tt_statereg[0]);
  INV  I204(I204, g203);
  OR2  g203(g203, g202, g201);
  AND2  g202(g202, g194, ac_ac_ttftop103Lt);
  AND2  g201(g201, ac_ac_node_startLLLLLLLLLt, g194);
  OR2  g200(g200, g199, g196);
  OR2  g199(g199, g198, g197);
  AND2  g198(g198, g181, ac_ac_ttftop106LtLLLL);
  AND2  g197(g197, I195, ac_ac_ttftop103Lt);
  AND2  g196(g196, ac_ac_node_startLLLLLLLLLt, I195);
  INV  I195(I195, g194);
  AND2  g194(g194, I148, g193);
  AND2  g193(g193, g192, I150);
  AND2  g192(g192, I152, g191);
  AND2  g191(g191, I154, g190);
  AND2  g190(g190, g189, I156);
  AND2  g189(g189, g188, I158);
  AND2  g188(g188, g187, I160);
  AND2  g187(g187, g186, I162);
  AND2  g186(g186, g185, I164);
  AND2  g185(g185, I168, I166);
  INV  I184(I184, g183);
  AND2  g183(g183, I182, ac_ac_ttftop106LtLLLL);
  INV  I182(I182, g181);
  AND2  g181(g181, I148, g180);
  AND2  g180(g180, g179, I150);
  AND2  g179(g179, g178, I152);
  AND2  g178(g178, g177, I154);
  AND2  g177(g177, g176, I156);
  AND2  g176(g176, I158, g175);
  AND2  g175(g175, g174, I160);
  AND2  g174(g174, g173, I162);
  AND2  g173(g173, I164, g172);
  AND2  g172(g172, I166, g171);
  AND2  g171(g171, I168, I170);
  INV  I170(I170, g169);
  XOR2  g169(g169, g135, i[4]);
  INV  I168(I168, g167);
  XOR2  g167(g167, g136, i[5]);
  INV  I166(I166, g165);
  XOR2  g165(g165, g137, i[6]);
  INV  I164(I164, g163);
  XOR2  g163(g163, g138, i[7]);
  INV  I162(I162, g161);
  XOR2  g161(g161, g139, i[8]);
  INV  I160(I160, g159);
  XOR2  g159(g159, g140, i[9]);
  INV  I158(I158, g157);
  XOR2  g157(g157, g141, i[10]);
  INV  I156(I156, g155);
  XOR2  g155(g155, g142, i[11]);
  INV  I154(I154, g153);
  XOR2  g153(g153, g143, i[12]);
  INV  I152(I152, g151);
  XOR2  g151(g151, g144, i[13]);
  INV  I150(I150, g149);
  XOR2  g149(g149, g145, i[14]);
  INV  I148(I148, g147);
  XOR2  g147(g147, g146, i[15]);
  AND2  g146(g146, g145, i[14]);
  AND2  g145(g145, g144, i[13]);
  AND2  g144(g144, g143, i[12]);
  AND2  g143(g143, g142, i[11]);
  AND2  g142(g142, g141, i[10]);
  AND2  g141(g141, g140, i[9]);
  AND2  g140(g140, g139, i[8]);
  AND2  g139(g139, g138, i[7]);
  AND2  g138(g138, g137, i[6]);
  AND2  g137(g137, g136, i[5]);
  AND2  g136(g136, g135, i[4]);
  AND2  g135(g135, g134, i[3]);
  AND2  g134(g134, g133, i[2]);
  AND2  g133(g133, i[1], i[0]);
  INV  I132(I132, cx_reset);
  DFF  i0chold_1002100(chold_1002[0], ctrlout, clk, LVCC, LGND, LGND);

endmodule


/* eof */

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