15 JJ Thomson Avenue
Cambridge, CB3 0FD, UK
I'm a PhD Student at the Computer Laboratory, University of Cambridge under the supervision of Peter Sewell, working on the semantics of concurrent ARM and POWER programs.
K. E. Gray, G. Kerneis, D. P. Mulligan, C.
Pulte, S. Sarkar, and P. Sewell.
An integrated concurrency and core-ISA architectural envelope
definition, and test oracle, for IBM POWER multiprocessors
[ pdf ]
- S. Flur, K. E. Gray, C. Pulte, S. Sarkar, A. Sezgin, L. Maranget, W. Deacon, and P. Sewell. Modelling the ARMv8 Architecture, Operationally: Concurrency and ISA
- S. Flur, S. Sarkar, C. Pulte, K. Nienhuis, L. Maranget, K. E. Gray, A. Sezgin, M. Batty, and P. Sewell Mixed-size Concurrency: ARM, POWER, C/C++11, and SC